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MPC8321EVRADDC 데이터시트(PDF) 43 Page - Freescale Semiconductor, Inc

부품명 MPC8321EVRADDC
상세설명  PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications
PDF  82 Pages
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제조업체  FREESCALE [Freescale Semiconductor, Inc]
홈페이지  http://www.freescale.com
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MPC8321EVRADDC 데이터시트(HTML) 43 Page - Freescale Semiconductor, Inc

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MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4
Freescale Semiconductor
43
UTOPIA
18 UTOPIA
This section describes the UTOPIA DC and AC electrical specifications of the MPC8323E.
NOTE
The MPC8321E and MPC8321 do not support UTOPIA.
18.1
UTOPIA DC Electrical Characteristics
Table 48 provides the DC electrical characteristics for the MPC8323E UTOPIA.
18.2
UTOPIA AC Timing Specifications
Table 49 provides the UTOPIA input and output AC timing specifications.
Table 48. UTOPIA DC Electrical Characteristics
Characteristic
Symbol
Condition
Min
Max
Unit
Output high voltage
VOH
IOH = –8.0 mA
2.4
V
Output low voltage
VOL
IOL = 8.0 mA
0.5
V
Input high voltage
VIH
—2.0
OVDD +0.3
V
Input low voltage
VIL
–0.3
0.8
V
Input current
IIN
0 V
≤ VIN ≤ OVDD
±5
μA
Table 49. UTOPIA AC Timing Specifications1
Characteristic
Symbol2
Min
Max
Unit
UTOPIA outputs—Internal clock delay
tUIKHOV
05.5
ns
UTOPIA outputs—External clock delay
tUEKHOV
18
ns
UTOPIA outputs—Internal clock high impedance
tUIKHOX
05.5
ns
UTOPIA outputs—External clock high impedance
tUEKHOX
18
ns
UTOPIA inputs—Internal clock input setup time
tUIIVKH
8—
ns
UTOPIA inputs—External clock input setup time
tUEIVKH
4—
ns
UTOPIA inputs—Internal clock input hold time
tUIIXKH
0—
ns
UTOPIA inputs—External clock input hold time
tUEIXKH
1—
ns
Notes:
1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings
are measured at the pin.
2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tUIKHOX symbolizes the UTOPIA
outputs internal timing (UI) for the time tUTOPIA memory clock reference (K) goes from the high state (H) until outputs (O) are
invalid (X).



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