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MPC8321EVRADDC 데이터시트(PDF) 13 Page - Freescale Semiconductor, Inc |
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MPC8321EVRADDC 데이터시트(HTML) 13 Page - Freescale Semiconductor, Inc |
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13 / 82 page ![]() MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4 Freescale Semiconductor 13 DDR1 and DDR2 SDRAM 6 DDR1 and DDR2 SDRAM This section describes the DC and AC electrical specifications for the DDR1 and DDR2 SDRAM interface of the MPC8323E. Note that DDR1 SDRAM is Dn_GVDD(typ) = 2.5 V and DDR2 SDRAM is Dn_GVDD(typ) = 1.8 V. The AC electrical specifications are the same for DDR1 and DDR2 SDRAM. 6.1 DDR1 and DDR2 SDRAM DC Electrical Characteristics Table 12 provides the recommended operating conditions for the DDR2 SDRAM component(s) of the MPC8323E when Dn_GVDD(typ) = 1.8 V. Table 13 provides the DDR2 capacitance when Dn_GVDD(typ) = 1.8 V. Input current IIN 0 V ≤ VIN ≤ OVDD — ±5 μA— Note: 1. This specification applies when operating from 3.3 V supply. Table 12. DDR2 SDRAM DC Electrical Characteristics for D n _GVDD(typ) = 1.8 V Parameter/Condition Symbol Min Max Unit Notes I/O supply voltage D n _GV DD 1.71 1.89 V 1 I/O reference voltage MVREF nREF 0.49 × Dn_GVDD 0.51 × Dn_GVDD V2 I/O termination voltage VTT MVREF nREF – 0.04 MVREF nREF +0.04 V 3 Input high voltage VIH MVREF nREF + 0.125 D n _GV DD +0.3 V — Input low voltage VIL –0.3 MVREF nREF – 0.125 V — Output leakage current IOZ –9.9 9.9 μA4 Output high current (VOUT = 1.35 V) IOH –13.4 — mA — Output low current (VOUT = 0.280 V) IOL 13.4 — mA — Notes: 1. D n _GV DD is expected to be within 50 mV of the DRAM Dn_GVDD at all times. 2. MVREF nREF is expected to be equal to 0.5 × Dn_GVDD, and to track Dn_GVDD DC variations as measured at the receiver. Peak-to-peak noise on MVREF nREF may not exceed ±2% of the DC value. 3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be equal to MVREF nREF. This rail should track variations in the DC level of MVREFnREF. 4. Output leakage is measured with all outputs disabled, 0 V ≤ VOUT ≤ Dn_GVDD. Table 13. DDR2 SDRAM Capacitance for D n _GVDD(typ) = 1.8 V Parameter/Condition Symbol Min Max Unit Notes Input/output capacitance: DQ, DQS CIO 68 pF 1 Table 11. Reset Signals DC Electrical Characteristics (continued) Characteristic Symbol Condition Min Max Unit Notes |
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