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MPC8321EVRADDC 데이터시트(PDF) 42 Page - Freescale Semiconductor, Inc |
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MPC8321EVRADDC 데이터시트(HTML) 42 Page - Freescale Semiconductor, Inc |
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42 / 82 page ![]() MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4 42 Freescale Semiconductor TDM/SI 17.2 TDM/SI AC Timing Specifications Table 47 provides the TDM/SI input and output AC timing specifications. Figure 33 provides the AC test load for the TDM/SI. Figure 33. TDM/SI AC Test Load Figure 34 represents the AC timing from Table 47. Note that although the specifications generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge is the active edge. Figure 34. TDM/SI AC Timing (External Clock) Diagram Input low voltage VIL — –0.3 0.8 V Input current IIN 0 V ≤ VIN ≤ OVDD —±5 μA Table 47. TDM/SI AC Timing Specifications1 Characteristic Symbol2 Min Max Unit TDM/SI outputs—External clock delay tSEKHOV 212 ns TDM/SI outputs—External clock High Impedance tSEKHOX 210 ns TDM/SI inputs—External clock input setup time tSEIVKH 5— ns TDM/SI inputs—External clock input hold time tSEIXKH 2— ns Notes: 1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings are measured at the pin. 2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tSEKHOX symbolizes the TDM/SI outputs external timing (SE) for the time tTDM/SI memory clock reference (K) goes from the high state (H) until outputs (O) are invalid (X). Table 46. TDM/SI DC Electrical Characteristics (continued) Characteristic Symbol Condition Min Max Unit Output Z0 = 50 Ω OVDD/2 RL = 50 Ω TDM/SICLK (Input) tSEIXKH tSEIVKH tSEKHOV Input Signals: TDM/SI (See Note) Output Signals: TDM/SI (See Note) Note: The clock edge is selectable on TDM/SI. tSEKHOX |
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