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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ORSPI4 데이터시트(PDF) 181 Page - Lattice Semiconductor |
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ORSPI4 데이터시트(HTML) 181 Page - Lattice Semiconductor |
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181 / 263 page  Lattice Semiconductor ORCA ORSPI4 Data Sheet 181 The static timing budget for a data transfer between two ORSPI4 devices at a data rate of 650 Mbps in shown in Table 61. Table 61. Data Path Interface Timing Example for Static Alignment (ORSPI4 to ORSPI4) Note 1: ORSPI4 Transmit Specification Note 2: ORSPI4 Receive Specification Description Value Unit TDCLK/RDCLK frequency 325 MHz Before reference point A 1 Clock to data skew, clock duty cycle distortion, data duty cycle distortion, data jitterTdia + Tdib 400 ps Between reference points A and B Data to data skew, relative jitter 100 ps Subtotal Gmax 500 ps After reference point B Device setup and hold 2 940 ps Sampling Error 50 ps Total 1490 ps Total 650 Mbps bit period 1540 ps Available margin 50 ps |
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