ORSPI4 datasheet(199/263 Pages) LATTICE

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Lattice Semiconductor

ORCA ORSPI4 Data Sheet

199

MPI_CLK

This is the PowerPC synchronous, positive-edge bus clock used for the

MPI interface. It can be

a source of the clock for the Embedded System Bus. If MPI is used this will be the AMBA bus

clock.

I/O If not used for MPI these pins are user-programmable I/O pins after conﬁguration.

MPI_TEA

A low on the MPI transfer error acknowledge indicates that the MPI detects a bus error on the

internal system bus for the current transaction.

I/O If not used for MPI these pins are user-programmable I/O pins after conﬁguration.

MPI_RTRY

This pin requests the MPC860 to relinquish the bus and retry the cycle.

I/O If not used for MPI these pins are user-programmable I/O pins after conﬁguration.

D[0:31]

I/O Selectable data bu

s width from 8, 16, 32-bit in MPI mode. Driven by the bus master in a write

transaction and driven by MPI in a read transaction.

D[7:0] receive conﬁguration data during master parallel, peripheral, and slave parallel conﬁgu-

ration modes when WR is low and each pin has a pull-up enabled. During serial conﬁguration

modes, D0 is the DIN input.

D[7:3] output internal status for asynchronous peripheral mode when RD is low.

I/O After conﬁguration, if MPI is not used, the pins are user-programmable I/O pins.

DP[0:3]

I/O Selectable parity bus width in MPI mode from 1, 2, 4-bit, DP[0] for D[0:7], DP[1] for D[8:15],

DP[2] for D[16:23], and DP[3] for D[24:31].

After conﬁguration, if MPI is not used, the pins are user-programmable I/O pin.

DIN

During slave serial or master serial conﬁguration modes, DIN accepts serial conﬁguration data

synchronous with CCLK. During parallel conﬁguration modes, DIN is the D0 input. During con-

ﬁguration, a pull-up is enabled.

I/O After conﬁguration, this pin is a user-programmable I/O pin.

DOUT

During conﬁguration, DOUT is the serial data output that can drive the DIN of daisy-chained

slave devices. Data out on DOUT changes on the rising edge of CCLK.

I/O After conﬁguration, DOUT is a user-programmable I/O pin.

TESTCFG

During conﬁguration this pin should be held high, to allow conﬁguration to occur. A pull up is

enabled during conﬁguration.

I/O After conﬁguration, TESTCFG is a user programmable I/O pin.

1. The FPGA States of Operation section in the ORCA Series 4 FPGAs data sheet contains more information on how to control these signals

during start-up. The timing of DONE release is controlled by one set of bit stream options, and the timing of the simultaneous release of all

other conﬁguration pins (and the activation of all user I/Os) is controlled by a second set of options.

Table 79. Pin Descriptions (Continued)

Symbol

I/O

Description

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