ORSPI4 datasheet(200/263 Pages) LATTICE

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Lattice Semiconductor

ORCA ORSPI4 Data Sheet

200

ORSPI4 SPI4 External I/O Description

This section describes device I/O signals to/from the SPI4 interface. Table 80 and Table 81 lists the external signals

that interface to the SPI4 block.

Table 80. SPI4 External Transmit Path Interface Signals

Table 81. SPI4 External Receive Path Interface Signals

Pin Name

(j = A or B)

Direction

O = FPSC Output

I = FPSC Input

Description

TSCLKj

LVTTL transmit status clock input.

TSTATj[1:0]

LVTTL transmit status input

jTSCLKN

LVDS (negative) transmit status clock input

jTSCLKP

LVDS (positive) transmit status clock input

jTSTATN[1:0]

LVDS (negative) transmit status data input

jTSTATP[1:0]

LVDS (positive) transmit status data input

jTDATN[15:0]

LVDS (negative) transmit SPI4 data output

jTDATP[15:0]

LVDS (positive) transmit SPI4 data output

jTCTLN

LVDS (negative) transmit SPI4 control signal output

jTCTLP

LVDS (positive) transmit SPI4 control signal output

jTDCLKN

LVDS (negative) transmit SPI4 clock reference.

(100 - > 450 MHz)

jTDCLKP

LVDS (positive) transmit SPI4 clock reference.

(100 - >450 MHz)

jTREFCLK

SPI4 clock reference input.

Pin Name

(j = A or B)

Direction

O = FPSC Output

I = FPSC Input

Description

RSCLKj

LVTTL receive status clock output.

RSTATj[1:0]

LVTTL receive status output

jRSCLKN

LVDS (negative) receive status clock output

jRSCLKP]

LVDS (positive) receive status clock output

jRSTATN[1:0]

LVDS (negative) receive status data output

jRSTATP[1:0

LVDS (positive) receive status data output

jRDATN[15:0]

LVDS (negative) receive SPI4 data input

jRDATP[15:0]

LVDS (positive) receive SPI4 data input

jRCTLN

LVDS (negative) receive SPI4 control signal input

jRCTLP

LVDS (positive) receive SPI4 control signal input

jRDCLKN

LVDS (negative) receive SPI4 clock reference.

(100 - >450 MHz)

jRDCLKP

LVDS (positive) receive SPI4 clock reference. (100 - >450 MHz)

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