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ORCA ORSPI4 Data Sheet

203

ORSPI4 Memory Controller External I/O Description

This section describes device I/O signals to/from the Memory Controller. Table 84 lists the external signals that

interface to the Memory Controller block.

Table 84. Memory Controller External Interface Signals

Pin Name

QDRII

SDRAM Pin

Name

Direction

O = FPSC Output

I = FPSC Input

Description

Interface to QDRII SDRAM

PMIK, PMIKN

K,K#

Clock for write data D, address SA, and enables W# and R#

PMID(35:0)

D(35:0)

Write data bus

PMIA(17:0)

SA(17:0)

Address bus

PMIWN

Write enable (active-LO)

PMIRN

Read enable (active-LO)

PMIC, PMICN

CQ,CQ#

Clock for read data Q

PMIQ(35:0)

Q(35:0)

Read data bus

REFCLK Source Inputs

MCREFCLK

Dedicated Memory Controller reference clock (HSTL)

ATREFCLK

-I

SPIA reference clock (LVTTL). Note that this signal also is fed to

the SPIA block.

BTREFCLK

-I

SPIB reference clock, (LVTTL). Note that this signal also is fed

to the SPIB block.

Other Signals

EXT_1K

Reference resistor. Connect to a 1.5 K

Ω ± 1% precision resistor

to ground. This current should handle a total of 700

μA.

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