ORSPI4 datasheet(120/263 Pages) LATTICE

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Lattice Semiconductor

ORCA ORSPI4 Data Sheet

120

The receiver section receives high-speed serial data at its differential CML input port and sends it in to the Clock

and Data Recovery (CDR) block. The CDR block then generates a recovered clock (RWCKx) and retimes the data.

Thus, the recovered receive clocks are asynchronous between channels.

Transmit Clock Source Selection

The TCKSEL[A:B] bit select the source channel of TCK78. The selection of the source for TCK78 is controlled by

this bit as shown in Table 32.

Table 32. TCK78 Source Selection

Recommended Transmit Clock Distribution for the ORSPI4

As an example of the recommended clock distribution approach, TSYS_CLK_[A:D] can be sourced by TCK78 as

shown in Figure 58 if the transmit line rate are common for all four channels in a quad.

Figure 58. Transmit Clocking for a Single Block

If the transmit line rate is mixed between half and full rate among the channels, then the scheme shown in Figure

59 can be used. The ﬁgure shows TSYS_CLK_A and TSYS_CLK_B being sourced by TCK78 and TSYS_CLK_C

and TSYS_CLK_D being sourced by TCK78/2 (the division is done in FPGA logic). Similar clocking would be used

for Quad B.

TCKSEL0

TCKSEL1

Clock Source

Channel A

Channel B

Channel C

Common Logic

Channel A

Channel B

Channel D

Channel C

REFCLK[P:N]

156.25 MHz

TCK78

TSYS_CLK_A

TSYS_CLK_C

TSYS_CLK_B

TSYS_CLK_D

FPGA

Logic

All Clocks at

78.125 MHz

Four Channels of

3.125 Gbits/s

Outgoing Serial Data

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