ORSPI4 datasheet(121/263 Pages) LATTICE

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Lattice Semiconductor

ORCA ORSPI4 Data Sheet

121

Figure 59. Mixed Rate Transmit Clocking for a Single Block

Receive Clock Source Selection and Recommended Clock Distribution

In the receive path, one clock per bank of four channels, called RCK78, is sent to the FPGA logic. The control reg-

ister bits RCKSEL[0:1] are used to select the clock source for these clocks. The selection of the source for RCK78

is controlled by these bits as shown in Table 33.

Table 33. RCK78 Source Selection

In the receive channel alignment bypass mode, the data and recovered clocks for the four channels are indepen-

dent. The data for each channel are synchronized to the recovered clock from that channel.

RCKSEL0

RCKSEL1

Clock Source

Channel A

Channel B

Channel C

Common Logic

Channel A

Channel B

Channel D

Channel C

REFCLK[P:N]

100 MHz

TCK78

TSYS_CLK_A

TSYS_CLK_C

TSYS_CLK_B

TSYS_CLK_D

FPGA

Logic

Two Channels of

2.0 Gbits/s (Full-Rate)

Outgoing Serial Data

Channel A Selected as

Clock Source

50 MHz

÷ 2

25 MHz

Two Channels of

1.0 Gbits/s (Half-Rate)

Outgoing Serial Data

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