ORSPI4 datasheet(122/263 Pages) LATTICE

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Lattice Semiconductor

ORCA ORSPI4 Data Sheet

122

Figure 60. Receive Clocking for a Single Quad

Figure 61. Receive Clocking for Mixed Line Rates

Multichannel Alignment

The alignment FIFO allows the transfer of all data to the system clock. The Multi-Channel Alignment block (Figure

52) allows the system to be conﬁgured to allow the frame alignment of multiple, slightly varying, data streams. This

optional alignment ensures that matching SERDES streams will arrive at the FPGA in perfect data synchronization.

Each channel is provided with a 24 word x 36-bit FIFO. The FIFO can perform two tasks: (1) to change the clock

domain from receive clock to a clock on the FPGA side, and (2) to align the receive data over 2, 4, or 8 channels.

This FIFO allows a timing budget of +/- 230.4 ns that can be allocated to skew between the data lanes and for

transfer to the system clock. The input to the FIFO consists of 36-bits of demultiplexed data, RALIGN_x[3:0],

RWD_x[31:0], and RWBIT8_x[3:0].

The four RALIGN_x bits are control signals, and can be the alignment character detect signals, indicating the pres-

ence of a comma character in Fibre Channel mode and the /A/ character in XAUI mode. The other 32 RWD_x bits

are the 8-bit data bytes from the 8b/10b decoder. The alignment character, if present, is the MSB of the data. The

Common Logic

Channel A

Channel B

Channel D

Channel C

REFCLK[P:N]

156.25 MHz

RCK78

RWCKA

RWCKC

RSYS_CLK_1

RSYS_CLK_2

FPGA

Logic

Four Channels of

3.125 Gbits/s

Incoming Serial Data

78.125 MHz

RWCKB

RWCKD

All Recovered

Clocks at

78.125 MHZ

Common Logic

Channel A

Channel B

Channel D

Channel C

REFCLK[P:N]

100 MHz

RCK78

RWCKA

RWCKC

RSYS_CLK_1

RSYS_CLK_2

FPGA

Logic

Two Channels of

2.0 Gbits/s (Full-Rate)

Incoming Serial Data

25 MHz

RWCKB

RWCKD

Recovered

Clocks at

25 MHZ

or 50 MHz

Recovered

Clocks at

50 MHZ

Two Channels of

1.0 Gbits/s (Half-Rate)

Incoming Serial Data

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