ORSPI4 datasheet(124/263 Pages) LATTICE

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Lattice Semiconductor

ORCA ORSPI4 Data Sheet

124

Figure 64. Deskew Lanes by Aligning /A/ Columns

SERDES/FPGA Interface

This block provides the data formatting and receive data and clock signal transfers between the SERDES and the

FPGA Logic. There are also control and status registers in the FPGA portion of the chip, which contain bits to con-

trol the receive logic and to record status. These are described in later sections of this Data Sheet and communi-

cate with the core using the System Bus.

The demultiplexed, receive word outputs to the FPGA are shown in Figure 52. These are each 40 bits wide. There

are four of these interfaces, one for each SERDES channel. Each consist of four groups of 10-bit data or four

groups of decoded information depending on setting of 8b10bR_x control register bits.

Each 10-bit group of decoded information includes 8 bits of data and a one-bit K_CTRL indicator derived from the

received data, and a tenth bit of status information. The function of the tenth bit varies from group to group and

includes code violation, out of synchronization (OOS) indicators and the CH248_SYNC_x status bit.

CH248_SYNC_x indicates the status of multi-channel alignment of channel x and is high when the count for the

multi-channel alignment block reaches zero, regardless of whether or not multi-channel alignment is successful.

The mapping of the 10-bit groups to the MRWD_x[39:0] bits output to the FPGA logic is summarized in Table 34

and Table 35. The various functions of the bits that vary from channel to channel, i.e., bits 29 and 19, are also

described in Table 35.

Table 34. Deﬁnition of Bits of MRWDx[39:0]

Bit Index

8b10bR=0

8b10bR=1

NOCHALGN[A:B]=1

CV_SELx=0

NOCHALGN[A:B]=1

CV_SELx=1

NOCHALGN[A:B]=0

CV_SELx=1

bit 9 of 10-bit data 3

CV_A3, code violation, byte 3

CH24_SYNCx

bit 8 of 10-bit data 3

K_CTRL for byte 3

bit 7 of 10-bit data 3

bit 7 of byte3

bit 6 of 10-bit data 3

bit 6 of byte 3

bit 5 of 10-bit data 3

bit 5 of byte 3

bit 4 of 10-bit data 3

bit 4 of byte 3

bit 3 of 10-bit data 3

bit 3 of byte 3

bit 2 of 10-bit data 3

bit 2 of byte 3

bit 1 of 10-bit data 3

bit 1 of byte 3

bit 0 of 10-bit data 3

bit 0 of byte 3

bit 9 of 10-bit data 2

CV_A2, code violation, byte 2

See

Table 35

bit 8 of 10-bit data 2

K_CTRL for byte 2

bit 7 of 10-bit data 2

bit 7 of byte 2

bit 6 of 10-bit data 2

bit 6 of byte 2

LANE 0

LANE 1

LANE 2

LANE 3

LANE 0

LANE 1

LANE 2

LANE 3

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