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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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PIFE32251B-R68MS 데이터시트(PDF) 20 Page - Texas Instruments |
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PIFE32251B-R68MS 데이터시트(HTML) 20 Page - Texas Instruments |
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20 / 157 page  20 TPS650830 SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 www.ti.com Submit Documentation Feedback Product Folder Links: TPS650830 Specifications Copyright © 2014–2016, Texas Instruments Incorporated Electrical Characteristics (continued) Over recommended free-air temperature range and over recommended input voltage range (typical at an ambient temperature range of 25°C) (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOH_PP High level output voltage IOH = 3 mA VDDIO - 0.6 V CONTROL - VDDPG DOMAIN PUSH-PULL OUTPUTS, (Optional: PGA, PGB, PGC, PGD, PGE, PGF, PGG, PGH) VPP Pull-up output voltage supply Pulled-Up to VDDPG pin VDDPG V VOL_PP Low level output voltage IOL = 3 mA 0.6 V VOH_PP High level output voltage IOH = 3 mA VDDPG - 0.6 V CONTROL - VDDLV DOMAIN PUSH-PULL OUTPUTS (Optional: LVA, LVB) VPP_VDDLV LV pull-up output voltage supply Pulled up to VDDLV pin VDDLV V VOL_PP_LV LV low level output voltage IOL = 3 mA 0.6 V VOH_PP_LV LV high level output voltage IOH = 3 mA VDDLV - 0.6 V CONTROL - GENERAL OPEN-DRAIN OUTPUTS, (ACSWONZ, BAT1SWONZ, BAT2SWONZ, VCCST_PWRGD, SYS_PWROK, PCH_PWROK, RSMRSTZ_PWRGD, ALL_SYS_PWRGD, PMIV_INTZ, EC_RSTZ, PCH_PWRBTNZ, EC_ONOFFZ, DPWROK) (Optional: PGA, PGB, PGC, PGD, PGE, PGF, PGG, PGH, PGVR1, PGVR2, PGVR3, PGVR4, PGVR5, LVA, LVB) VOL_OD1 OD- output voltage IOL = 2 mA 0.4 V ILK_OD1 OD leakage current V(PIN) = 3.3 V 0.45 μA CONTROL - OPEN-DRAIN OUTPUT (TEMP_ALERT) VOL_OD Open-drain low level output voltage IOL = 15 mA, with 75-Ω pull-up resistor to 1 V 0.165 V ILK_OD Open-drain leakage current V(PIN) = 3.3 V, with 75-Ω pull-up resistor to 1 V 0.35 μA CONTROL - TRISTATE INPUT BUFFER (SLAVEADDR, DDRID) VIL_TRISTATE Low level input voltage IOL = 6 μA 0.33 V VIH_TRISTATE High level input voltage IOH = 6 μA 1.8 V ITRISTATE ITRISTATE current Maximum allowable current in or out of pin when floating to maintain FLOAT logic state -0.650 0.675 μA ITRISTATE_TOTAL_ PIN_GND Total current drawn when pin connected to GND VINLDO3 current when TRISTATE pin = GND 6 μA ITRISTATE_TOTAL_ PIN_3.3V Total current drawn when pin connected to 3.3 V VINLDO3 current when TRISTATE pin = LDO3V = 3.3 V 6 μA ITRISTATE_TOTAL_ PIN_FLOAT Total current drawn when pin Floating VINLDO3 current when TRISTATE pin = Floating 4.5 μA CONTROL - VSA, VSB, VSC, VSD, VSE, VSF, VSG, VSH (EXTERNAL VR and EXTERNAL LOADSWITCH POWERGOOD COMPARATORS) VSx input voltage range When VSx configured as voltage sense input 0.7 1.8 5 V VSx input leakage current When VSx configured as voltage sense input, VSx = 5.7 V 0 9 μA Powergood exit threshold high VSx VSx rising out of powergood. When VSx configured as voltage sense input and powergood window comparator. 106% 108% 110% Powergood threshold high VSx hysteresis VSx falling into powergood. When VSx configured as voltage sense input and powergood window comparator. -3% Powergood exit threshold low VSx VSx falling out of powergood. When VSx configured as voltage sense input and powergood window comparator. 90% 92% 94% Powergood threshold low VSx hystersis VSx rising into powergood. When VSx configured as voltage sense input and powergood window comparator. 3% |
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