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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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PIFE32251B-R68MS 데이터시트(PDF) 64 Page - Texas Instruments |
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PIFE32251B-R68MS 데이터시트(HTML) 64 Page - Texas Instruments |
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64 / 157 page  0.90*VREF Vout (Enable) time PGVRx (Powergood) 30 us deglitch ENVRx PWRGD threshold 0 0 ENVRx FBVRxP (Vout) 1.10*VREF PGVRx Programmable Discharge Resistance 0 VREF Max LPM Exit time < 35us ENABLE VTT DDR_VTT_CTRL LDO1 VTT PG_VTT FB_VTT VOUTLDO1 FBLDO1 PGVRx ENABLE VDDQ ENVR4 VR4 VDDQ PG_VDDQ FB_VDDQ VOUT FBVR4P PGVR4 Lout Cout VDDQ VINLDO1 VINLDO1S FB_VDDQ Copyright © 2016, Texas Instruments Incorporated 64 TPS650830 SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 www.ti.com Submit Documentation Feedback Product Folder Links: TPS650830 Detailed Description Copyright © 2014–2016, Texas Instruments Incorporated 6.3.12 VR4 VDDQ and LDO1 VTT Enabling The VDDQ is enabled by the ENVR4 pin, while the LDO1 VTT push-pull LDO is enabled by the DDR_VTT_CTRL pin. The DDR_VTT_CTRL pin is often connected to the SLP_S0# pin to turn off during sleep mode. The DDRID pin is a tri-level pin that sets the VR4 VDDQ voltage to either 1.2 V, 1.35 V, or 1.1 V. DDR_VTT_CTRL pin ais also used for DVS control of VR4, as defined on register 0x36, V1P2UCNT. Figure 6-13. VR4 VDDQ and LDO1 VTT Enabling |
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