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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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PIFE32251B-R68MS 데이터시트(PDF) 45 Page - Texas Instruments |
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PIFE32251B-R68MS 데이터시트(HTML) 45 Page - Texas Instruments |
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45 / 157 page  VOLUME Application Block Diagram: VR1 = V1.00A (V11), & V085A (V12), VR2 = V1.8A (V8), VR3 = V33ADSW (V6), VR4 = V1.2U (V10), VR5 = V5ADS3 (V5) COMPA = V3.3A_PCH (V7), COMPB = V1.8U_2.5U (V9), COMPC = Generic Comparator, COMPD = VCCIO (V4), COMPE = V3.3S, COMPF = V1.8S, COMPG = V1.00S TPS650830 ± VOLUME G3 ÆS5/S4 G3 S5/S4 S5/S4 Æ S0 VOL#1 xxxx xxxx PG PG Assumes V1.8A enabled by DPWROK. Could also be enabled by SLP _SUS# later. xxx xxx xxx xxx xxx xxx xxx xxx xxx xxx xxx PG V5A_DS3_PG to V 1.00A_PG <20mSec >10ms delay from PG V3.3A_DSW to DPWROK V33ADSW (V6) [FBVR3P] DPWROK [DPWROK] V3.3A_DSW_PG (V6) [PGVR3] SLP_SUS# [ENE] V1.8A (V8) [FBVR2P] V1.8A_PG [PGVR2] V3.3A_DSW_EN (V6) [ENVR3] (Tie to LDO 3) V1.8A_EN (V8) [ENVR2] V5ADS3 (V5) [FBVR5P] V5ADS3_PG [PGVR5] DS3_VREN [DS3_VREN] V5ADS3_EN [ENVR5] DS3VREN is gated by V5ADS3_EN ~ 1us delay V5ADS3_EN is copy of SLP _SUS# PG >10mSec PG SLP_S4# to V1.2U ramp >2.5ms [4ms] PG PG PG PG PG Prog Prog PG 2ms (from the last PG ) 1.00V SLP_S4# to V1.8U_2.5U ramp = 0.5ms ” tdelay +tramp-up ” 2ms [Load Sw turn-on time] 1.00V No direct SLP_S3# connection SLP_S3# & V1.2U_PG & V1.00S_PG [V1.2U_PG & V1.00S_PG open-drain outputs drive same ENVR3 pin, with single pull-up resistor] SLP_S4# [ENB] RSMRST#_PWRGD [RSMRST#_PWRGD] V1.8U_2.5U (V9) [VSB] V1.2U (V10) [FBVR4P] SLP_S3# [ENF] for powergood tree only V1.8U_2.5U_PG [PMIC internal ] V1.2U_PG [PGVR4] V1.8U_2.5U_EN [PGB] V1.2U_EN [ENVR4] V1.00S [VSG] V3.3S [VSE] V100S_EN [ENG] ± to Load Switch V1.8S [VSF] V1.00S_PG [PGG] V3.3S_EN [ENG] ± to Load Switch V3.3S_PG [PMIC internal ] V1.8S_EN [ENG] ± to Load Switch V1.8S_PG [PGF] ALL_SYS_PWRGD [ALL_SYS_PWRGD] VCCST_PWRGD [VCCST_PWRGD] PCH_PWROK [PCH_PWROK] SYS_PWROK [SYS_PWROK] VCCIO (V4) [VSD] VCCIO_EN [PGD] ± to Load Switch VCCIO_PG [PMIC internal ] RSMRST# [RSMRST#] V3.3APCH (7) [VSA] V33APCH_EN_qualified [PGE] ± to Load Switch V3.3APCH_PG [PGA] V085A (V12) / V100A (V11) [FBVR1P] V085A_EN / V100A_EN [ENVR1] V085A_PG / V100A_PG [PGVR1] V33APCH_EN_control [ENA] xxxx xxxx VREF1V25 UVLO3# [UVLO2#_LDO3EN] LDO3 VDC (BAT/ADP Insertion ) LDO3_PG I2C Ready PMIC I2C UVLO5# [UVLO1#_LDO5EN] (Power On Dig Reset ) LDO5_PGD LDO5 OTP_LOAD 1ms from UVLO5/Dig Reset to OTP Loaded 3.1V LDO Vcoin_cell_battery V3P3A_RTC [V3P3A_RTC] 3.2V 2.0V ext ext ext ext internal external int ext ext ext ext ext ext int 95ms DPWROK to SLP_SUS# takes 95ms from PCH 16ms 45 TPS650830 www.ti.com SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 Submit Documentation Feedback Product Folder Links: TPS650830 Specifications Copyright © 2014–2016, Texas Instruments Incorporated Figure 5-1. TPS650830 Volume Timing Diagram |
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