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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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PIFE32251B-R68MS 데이터시트(PDF) 9 Page - Texas Instruments |
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PIFE32251B-R68MS 데이터시트(HTML) 9 Page - Texas Instruments |
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9 / 157 page  9 TPS650830 www.ti.com SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 Submit Documentation Feedback Product Folder Links: TPS650830 Pin Configuration and Functions Copyright © 2014–2016, Texas Instruments Incorporated (1) VR – VR Critical, AS – Analog Sensitive, D – Digital, A - AGND 4.1 Pin Functions Table 4-1. Pin Functions PIN I/O TYPE(1) DESCRIPTION NAME ZAJ PACKAGE NUMBER ZCG PACKAGE NUMBER ACIN E2 H3 I AS AC Adaptor voltage sense ACOK D11 F13 I D ACOK input ACSWONZ J2 M3 O D AC adaptor switch ON power-path (Open-drain output) (active low) AGND F8, G8, H8, J8, F7, G7, H7, J7, K7, F6, G6, H6, J6, K6, G5, H5, J5 - - A Analog GND - tie directly to the ground plane AGND1 C1 E1 - A Analog GND1 - tie directly to the ground plane AGND2 K1 N1 - A Analog GND2 - tie directly to the ground plane AGND3 L13 N16 - A Analog GND3 - tie directly to the ground plane AGND4 D13 E16 - A Analog GND4 - tie directly to the ground plane ALL_SYS_PWRGD G11 F15 O D Non-core rails powergood, All PMIC and specified monitored VRs power good (Open-drain output) BAT1 F1 H1 I AS Battery 1 voltage sense input BAT2 G1 J1 I AS Battery 2 voltage sense input BAT1SWONZ F2 J2 O D Battery 1 switch ON power-path (Open-drain output) (active low) BAT2SWONZ G2 K3 O D Battery 2 switch ON power-path (Open-drain output) (active low) DDRID D4 C2 I D VR4 Output voltage selection. Low = 1.2 V, High = 1.35 V, Float = 1.1 V. DDR_VTT_CTRL E3 E4 I D LDO1 Enable, and DVS control of VR4 DPWROK K12 M15 O D Delayed version of V3.3A_DSW_PG (Open-drain output) DRVHVR1 N12 T14 O VR VR1 High side gate drive output (external power FET) DRVHVR3 A12 A14 O VR VR3 High side gate drive output (external power FET) DRVHVR4 A2 A3 O VR VR4 High side gate drive output (external power FET) DRVHVR5 M1 T3 O VR VR5 High side gate drive output (external power FET) DRVLVR1 N9 T11 O VR VR1 Low side gate drive output (external power FET) DRVLVR3 A9 A11 O VR VR3 Low side gate drive output (external power FET) DRVLVR4 A5 A6 O VR VR4 Low side gate drive output (external power FET) DRVLVR5 N4 T6 O VR VR5 Low side gate drive output (external power FET) DS3_VREN K13 M16 O D DS3 VR enable (enables external power switches) (Push-pull output) ECVCC L1 P1 I AS EC VCC supply EC_ONOFFZ K4 M5 O D Debounced version of PWRBTNIN (Open-drain output) (active low) EC_RSTZ J3 L4 O D EC reset (Open-drain output) (active low) ENA B12 B15 I D Enable for VSA powergood comparator ENB C11 D13 I D Enable for VSB powergood comparator ENC C12 D15 I D Enable for VSC powergood comparator END J13 L16 I D Enable for VSD powergood comparator ENE F10 J12 I D Enable for VSE powergood comparator ENG B10 C14 I D Enable for VSG powergood comparator ENF J12 L14 I D Enable for VSF powergood comparator ENH L11 P13 I D Input to Level Shifter B general purpose level shifter. ENLVA L6 P5 I D Enable level shifter A. Pin not used for TPS650830. Connect to ground if unused. (Level Shifter A input is ACOK pin) |
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