PIFE32251B-R68MS datasheet(28/157 Pages) TI1

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TPS650830

SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016

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Specifications

Electrical Characteristics (continued)

Over recommended free-air temperature range and over recommended input voltage range (typical at an ambient

temperature range of 25°C) (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DVS slew rate for falling edge

DVS falling edge slew rate for VVOUT to

change from the upper target to the lower

target after STANDBYZ (SLP_S0#)

changes from High to Low. Total ramp

time = ((Vout_high - Vout_low) /

slew_rate)

4.5

5.5

mV / μs

DVS total rise time (delay time +

output ramp-rise time)

Time to start switching from enable to

95% of VO(Min), Continuous slope (no

slope reversal).

61.25

68.5

μs

DVS delay time for rising edge

DVS delay time from when STANDBYZ

(SLP_S0#) changes from Low to High,

until the output voltage begins to rise.

1.25

1.5

μs

DVS ramp time for rising edge

From first switching pulse to 95% of

VO(Min), Continuous slope (no slope

reversal). Total ramp time = ((Vout_high -

Vout_low) / slew_rate). For Vout change

= 300 mV

μs

DVS slew rate for rising edge

DVS rising edge slew rate for VVOUT to

change from the lower target to the upper

target after STANDBYZ (SLP_S0#)

changes from Low to High. Total ramp

time = ((Vout_high - Vout_low) /

slew_rate).

4.5

5.5

mV / μs

Output auto discharge resistance

Discharge register value

DISCHGCNT3[7:6]: 00, Default

250

860

1450

kΩ

Output auto discharge resistance

Discharge register value

DISCHGCNT3[7:6]: 01

100

120

Output auto discharge resistance

Discharge register value

DISCHGCNT3[7:6]: 10

160

200

240

Output auto discharge resistance,

Default

Discharge register value

DISCHGCNT3[7:6]: 11

400

500

600

Feedback input resistance

Enabled

MΩ

Quiescent current associated with

converter when enabled

IVout = 0 mA, enabled, at TA = 25°C Not

switching, Measured at LDO3V,

VREGVR2

μA

VR2 Converter CONTROL

Powergood exit threshold high

Fail when Vout increasing

106%

108%

110%

Powergood threshold high

hysteresis

Good when Vout decreases (after a

PGOOD fail event)

-3%

Powergood exit threshold low

Fail when Vout decreasing

90%

92%

94%

Powergood threshold low

hysteresis

Good when Vout increases (after a

PGOOD fail event)

VR2_Powergood deglitch time for

both rising and falling edges

FBVR2P voltage must cross powergood

threshold and stay for at least this time to

change powergood output state.

Measured from FBVR2P into or out of

powergood threshold, until PGVR2

toggles, for both rising and falling edges.

μs

VR2_Powergood Mask time during

and after soft-start ramp-up time

Powergood is kept low and power fault is

masked during soft-start until 100 µs after

the internal reference has stepped up to

the final voltage setting.

VR2_Powergood Mask time during

DVS ramp down (enter DVS)

Powergood is kept high and masked

during DVS enter, ramp down, and until

100 µs after the internal reference has

stepped down to the final voltage setting.

ramp-

down +

ramp-

down +

100

ramp-

down +

110

μs

PIFE32251B-R68MS 데이터시트(PDF) 28 Page - Texas Instruments

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