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PIFE32251B-R68MS 데이터시트(PDF) 68 Page - Texas Instruments |
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PIFE32251B-R68MS 데이터시트(HTML) 68 Page - Texas Instruments |
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68 / 157 page ![]() 68 TPS650830 SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 www.ti.com Submit Documentation Feedback Product Folder Links: TPS650830 Detailed Description Copyright © 2014–2016, Texas Instruments Incorporated 6.3.13.5 Output Discharge Feature All the voltage regulators have a built in output discharge feature. The output discharge feature consists of being able to configure register bits to enable a discharge resistor which is only active whenever the voltage regulator is disabled. The discharge resistors for each of the voltage regulators can be configured using the DISCHCNT1, DISCHCNT2, DISCHCNT3 and DISCHCNT4 registers. The discharge resistors are disconnected when the voltage regulators are enabled in order to minimize any losses within the PMIC. 6.3.13.6 Output Voltage Control All voltage regulators are designed to regulate a fixed output voltage. To achieve high accuracy the output voltage for the converters and controller is sensed using a separate feedback pin. For each of the voltage rails, except for the VTT LDO, the output voltage can be changed to slightly higher or lower values by changing the default setting in the voltage regulator control registers (see section on the Voltage Regulator Voltage Options). This function can be used to save power when supplying the connected load at its minimum possible supply voltage or to compensate for voltage drops during load transients by programming it slightly higher. In addition the range of the output voltage for the regulators is highly programmable. If you need a different output voltage configuration from the specified default, please contact TI to generate you a custom part. 6.3.13.7 Converter Low Power Mode Operation For optimizing low power operation, the output voltage of the converters can be set to a specific value. The low power output voltage is set by the specific register and bits shown in the Voltage Regulator Voltage Options tables. Entering the low power mode is accomplished by asserting the SLP_S0# signal to a logic low. In this low power mode, the powergood function remains active and is not affected by the transition from normal operation mode to the low power mode and vice versa. 6.3.13.8 Controller Low Power Mode Operation For optimizing low power operation, the output voltage of the controllers can be set to a specific value. The low power output voltage is set by the specific register and bits shown in the Voltage Regulator Voltage Options tables. Entering the low power mode is accomplished by asserting the DDR_VTT_CTRL pin or the STANDBYZ pin to a logic low. In this low power mode, the powergood function remains active and is not affected by the transition from normal operation mode to the low power mode and vice versa. DDR_VTT_CTRL pin asserts DVS on VR4, while STANDBYZ pin asserts DVS in VR1, VR2, VR3, and VR5, as defined by ther CNT registers. In situations where the output current demand from the controller is very small, the controller is automatically placed in an Ultra Low Quiescent (ULQ) mode to reduce power consumption and increase the efficiency. 6.3.13.9 Controller Internal Ramp Comparator The controllers have an internal ramp, characteristic of th DCAP2 control architecture, to give improved performance with low-ESR output capacitors. This internal ramp provides ramp compensation that helps maintain a relatively constant frequency during CCM, and it provides better stability for designs with very low ESR on the output capacitors. The ramp height can be optimized and is a function of the input voltage to provide proportional feed-forward. At very high voltages, the ramp may exceed the operating window of the PWM comparator and may overpower the natural ripple of the output, so there is a need to switch to a smaller ramp. As the ramp was already getting large, it helps to switch back to a smaller size. To achieve this, a comparator monitors the input voltage at the VIN pin. When input voltage rises and exceeds 11 V, it changes the ramp to a slightly smaller value. There is a wide 1.1-V hysteresis, so at approximately 9.9 V as the Vin falls, the ramp returns to the slightly bigger size. In most cases this difference is negligible. |
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