PIFE32251B-R68MS datasheet(32/157 Pages) TI1

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TPS650830

SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016

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Specifications

Electrical Characteristics (continued)

Over recommended free-air temperature range and over recommended input voltage range (typical at an ambient

temperature range of 25°C) (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Output auto discharge resistance,

Default

Discharge register value: 11

450

550

690

VR3_Controller feedback input

resistance

Controller enabled

2.25

Ω

VR3_Bootstrap switch ON

resistance (Rdson)

TA = 25°C

VR3_Controller HSD leakage

VIN = 7.4 V, Controller disabled

1.55

μA

VR3 Controller CONTROL

VR3_Powergood exit threshold

high

Fail when Vout increasing

105.5%

108%

110.5%

VR3_Powergood threshold high

hysteresis

Good when Vout decreases (after a

PGOOD fail event)

-3%

VR3_Powergood exit threshold low Fail when Vout decreasing

89.5%

92%

94.5%

VR3_Powergood threshold low

hysteresis

Good when Vout increases (after a

PGOOD fail event)

VR3_Powergood deglitch time for

both rising and falling edges

FBVR3P voltage must cross powergood

threshold and stay for at least this time to

change powergood output state.

Measured from FBVR3P into or out of

powergood threshold, until PGVR3

toggles, for both rising and falling edges.

μs

VR3_Powergood Mask time during

and after soft-start ramp-up time

Powergood is kept low and power fault is

masked during soft-start until 100 µs after

the internal reference has stepped up to

the final voltage setting.

VR3_Powergood Mask time during

DVS ramp down (enter DVS)

Powergood is kept high and masked

during DVS enter, ramp down, and until

100 µs after the internal reference has

stepped down to the final voltage setting.

ramp-

down +

ramp-

down +

100

ramp-

down +

110

μs

VR3_Powergood Mask time during

DVS ramp up (exit DVS)

Powergood is kept high and masked

during DVS exit, ramp up, and until 100

µs after the internal reference has

stepped up to the final voltage setting.

ramp-

up + 90

ramp-

up +

100

ramp-

up +

110

μs

VR3_Powergood Mask time during

Decay

Powergood is kept high and masked

during Decay enter, during decay, exit,

ramp up, and until 100 µs after the

internal reference has stepped up to the

final voltage setting.

decay +

180

decay+

200

decay +

220

μs

VR3_Force PWM time (deglitch

time) during CCM to DCM

transition

PWM is forced for 16 switching cycles

before PFM is enabled turning off the low-

side power MOSFET. Low-side FET

current during each cycle must fall below

the PFM current comparator valley

threshold. Forced PWM allows a fast

transient response and smaller output

voltage ripple during the transition.

cycles

VR3_Force PWM time during DVS

ramp down (enter DVS)

PWM is forced during DVS enter, ramp

down, and until 10 µs after the internal

reference has stepped down to the final

voltage setting. Forced PWM allows a fast

transient response and smaller output

voltage ripple during the transition.

ramp-

down +

ramp-

down +

ramp-

down +

μs

VR3_Force PWM time during DVS

ramp up (exit DVS)

PWM is forced during DVS exit, ramp up,

and until 10 µs after the internal reference

has stepped up to the final voltage

setting. Forced PWM allows a fast

transient response and smaller output

voltage ripple during the transition.

ramp-

up + 9

ramp-

up + 10

ramp-

up + 11

μs

PIFE32251B-R68MS 데이터시트(PDF) 32 Page - Texas Instruments

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