PIFE32251B-R68MS datasheet(72/157 Pages) TI1

72 / 157 page

TPS650830

SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016

www.ti.com

Submit Documentation Feedback

Product Folder Links: TPS650830

Detailed Description

•

PWRBTNIN falling edge detected

•

ACOK transitions from LOW to HIGH

•

VIN < UVLO

Emergency Shutdown is initiated when:

•

VR Fault detected - Read RESETIRQ1 to determine if VR fault caused shutdown.

•

Hardware force shutdown

•

Software force shutdown

•

Die Thermal Fault - Read RESETIRQ2 to determine if thermal fault caused shutdown.

•

PWRBTN held longer than defined time by FLT[5:0] - Read RESETIRQ1 to determine if push button

caused shutdown.

•

VIN < UVLO - Read IRQLVL1 bit 2 to determine if VIN < UVLO caused shutdown.

6.4.10 Backup Battery / G3 - No VIN

G3 is an Intel defined state where the VIN < UVLO to the device but, a valid backup battery is present on

VBATTBKUP pin. In this state, the backup battery is passed to the RTC output and the RTC domain I2C

I2C is ready.

In this state, all VRs and internal LDOs are off and I2C access is not available.

6.5

Programming

6.5.1

2C - Interface

I2C is a 2-wire serial interface developed by NXP (formerly Philips Semiconductor) (see I2C-Bus

Specification and user manual, Rev 4, 13 February 2012). The bus consists of a data line (SDA) and a

clock line (SCL) with pull-up structures. When the bus is idle, both SDA and SCL lines are pulled high. All

the I2C compatible devices connect to the I2C bus through open drain I/O pins, SDA and SCL. A master

device, usually a microcontroller or a digital signal processor, controls the bus. The master is responsible

for generating the SCL signal and device addresses. The master also generates specific conditions that

indicate the START and STOP of data transfer. A slave device receives and/or transmits data on the bus

under control of the master device.

The TPS650830 works as a slave and supports the following data transfer modes, as defined in the I2C-

Bus Specification: standard mode (100 kbps), fast mode (400 kbps). The interface adds flexibility to the

power supply solution, enabling most functions to be programmed to new values depending on the

instantaneous application requirements. Register contents are loaded when voltage is applied to

TPS650830 higher than the undervoltage lockout threshold. The I2C interface is running from an internal

oscillator that is automatically enabled when there is an access to the interface.

The data transfer protocol for standard and fast modes is exactly the same, therefore, they are referred to

as F/S-mode in this document.

The TPS650830 supports 7-bit addressing; 10-bit addressing and general call address are not supported.

The default device address is defined by the status of the SLAVEADDR pin. 3 different slave addresses

are possible, 0x30 (SLAVEADDR 0 V), 0x32 (SLAVEADDR 3.3 V) and 0x34 (SLAVEADDR floating).

All registers are set to their default value when the supply voltage is below the UVLO threshold.

6.5.1.1

F/S-Mode Protocol

The master initiates data transfer by generating a start condition. The start condition is when a high-to-low

transition occurs on the SDA line while SCL is high, see Figure 6-17. All I2C-compatible devices should

recognize a start condition.

PIFE32251B-R68MS 데이터시트(PDF) 72 Page - Texas Instruments

PIFE32251B-R68MS 데이터시트(HTML) 72 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL