PIFE32251B-R68MS datasheet(67/157 Pages) TI1

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TPS650830

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SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016

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Detailed Description

6.3.13.3 Powergood, Power Fault, and Emergency Power Shutdown

During operation, when the voltage regulators are enabled, the output voltage for each rail is monitored in

order to assess if the output voltage is within a specified voltage range. A powergood status bit is

generated and stored in the PGOOD_STAT1 and PGOOD_STAT2 registers. If the output voltage is within

the specified voltage range, the respective powergood status bit is set to a logic high. If the output voltage

falls below or goes above the specified voltage range, the powergood status bit will be set to a logic low.

By default, if any of the output voltage rails experience a power fault condition, the PMIC will automatically

shutdown in order to protect the system unless the power fault is masked. If a power fault occurs, the

source of the power fault is maintained in the PWRSTAT1 and PWRSTAT2 registers which are

maintained in the RTC domain. The voltage thresholds for each of the powergood comparators is a

percentage relative to the nominal voltage setting of the output voltage - see the parametric table for each

voltage regulator powergood for the USL and LSL limits of the powergood comparators.

If a particular voltage rail is not critical to the performance of the overall system, the respective powergood

output can be masked using the PGMASK1 and PGMASK2 registers. The masking of a power fault will

inhibit an automatic PMIC shutdown. This can be also very helpful for debug purposes in case of system

failure to isolate the voltage regulator with the sensitive output voltage.

In order to avoid an erroneous power fault during the turn-on of the voltage regulators, the power fault is

masked for 10 ms relative to the enable whether it be from the discrete signal or from an I2C command.

powergood is also masked when coming out of sleep (S3 state) for 100 µs after the ALL_SYS_PWRGD

pin goes high to ensure that there is no false triggering of the powergood comparators.

The PMIC will only cause a Emergency Power Shutdown of the rails for the conditions shown in the table

below. The PMIC monitors each rail and ensures there is no problem. All rails are monitored for fault

protection, except for V3.3A_DSW and V5A external voltage regulators. The V3.3A_DSW and V5A have

no effect on Power Fault and cannot cause a shutdown, unless either one affects another rail. Notice also,

that the current limit (OCP) does not directly cause a shutdown. Instead, OCP could cause a shutdown

indirectly by means of a Power Fault. The OCP will limit the maximum possible output current, such that if

the load current exceeds the Ilim, then the voltage will drop, until eventually the lower output voltage

causes a Power Fault if it is below the powergood threshold for more than 30 µs. Emergency Power

Shutdown causes all rails to power-down within 1 us. The LDO3, LDO5, and VREF1.25V will stay up if the

input voltage is greater than the UVLO3 and UVLO5.

Table 6-2. All Possible Emergency Power Shutdown Conditions

SHUTDOWN CONDITION

VIN pin

≤ UVLO5V

VINLDO3 pin

≤ UVLO3V

Powergood Fault (OVP, UVP): Vout

≤ 90% or Vout ≥ 110% for ≥ 30 µs

≥ Tcritical (OTP)

SHUTDOWNZ pin pulled-low

I2C Control Force Shutdown by SDWNCTRL register (address = 0x49)

6.3.13.4 Current Limit

All voltage regulators are current limited, the current limit can be set based on the application load current

using an external resistor for all VRs except for VR2 which has an internally set current limit as it has an

integrated power stage. The current limit controls the maximum output current. If the maximum current is

reached, the output voltage will start to droop since the load can no longer be supplied with sufficient

power. If the voltage drops below the powergood threshold, the power fault status will be set to a logic

high and if the power fault is not masked, the PMIC will automatically shutdown in a controlled manner to

protect the system.

PIFE32251B-R68MS 데이터시트(PDF) 67 Page - Texas Instruments

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