 |
전자부품 데이터시트 검색엔진 |
|
|
전자부품 데이터시트 검색엔진 |
|
PIFE32251B-R68MS 데이터시트(PDF) 37 Page - Texas Instruments |
|
|
|||||||||||||||||||||||||||||
PIFE32251B-R68MS 데이터시트(HTML) 37 Page - Texas Instruments |
|
|
37 / 157 page  37 TPS650830 www.ti.com SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 Submit Documentation Feedback Product Folder Links: TPS650830 Specifications Copyright © 2014–2016, Texas Instruments Incorporated Electrical Characteristics (continued) Over recommended free-air temperature range and over recommended input voltage range (typical at an ambient temperature range of 25°C) (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VR4_Powergood Mask time during DVS ramp up (exit DVS) Powergood is kept high and masked during DVS exit, ramp up, and until 100 µs after the internal reference has stepped up to the final voltage setting. ramp- up + 90 ramp- up + 100 ramp- up + 110 μs VR4_Force PWM time (deglitch time) during CCM to DCM transition PWM is forced for 16 switching cycles before PFM is enabled turning off the low- side power MOSFET. Low-side FET current during each cycle must fall below the PFM current comparator valley threshold. Forced PWM allows a fast transient response and smaller output voltage ripple during the transition. 16 16 16 cycles VR4_Force PWM time during DVS ramp down (enter DVS) PWM is forced during DVS enter, ramp down, and until 10 µs after the internal reference has stepped down to the final voltage setting. Forced PWM allows a fast transient response and smaller output voltage ripple during the transition. ramp- down + 9 ramp- down + 10 ramp- down + 11 μs VR4_Force PWM time during DVS ramp up (exit DVS) PWM is forced during DVS exit, ramp up, and until 10 µs after the internal reference has stepped up to the final voltage setting. Forced PWM allows a fast transient response and smaller output voltage ripple during the transition. ramp- up + 9 ramp- up + 10 ramp- up + 11 μs Overtemperature protection 130 145 160 °C Overtemperature hysteresis 10 °C LDO1 POWER Input voltage DDRID = 0 V 1.2 V Output voltage DDRID = 0 V, VOUTLDO1 = (VINLDO1S) / 2 0.6 V Input voltage DDRID = 3.3 V 1.35 V Output voltage DDRID = 3.3 V, VOUTLDO1 = (VINLDO1S) / 2 0.675 V Input voltage DDRID = Open 1.1 V Output voltage DDRID = Open, VOUTLDO1 = (VINLDO1S)/ 2 0.55 V Output voltage tolerance - AC and DC transient load IOUT ≤ 10 mA, 1.1 V ≤ VINLDO1 ≤ 1.35 V, (FBLDO1 - FBVR4N) = Output voltage relative to (VINLDO1S - FBVR4N) / 2, where VINLDO1S connected to FBVR4P on the board, Load transient from 0mA to 70%*10 mA, dI/dt = 2.5 A/µs. -20 20 mV IOUT ≤ 1 A, 1.1 V ≤ VINLDO1 ≤ 1.35 V, (FBLDO1 - FBVR4N) = Output voltage relative to (VINLDO1S - FBVR4N) / 2, where VINLDO1S connected to FBVR4P on the board, Load transient from 0mA to 70%*1A, dI/dt = 2.5 A/µs. -30 30 mV Leakage current TA = 25°C, VINLDO1 = 1.2 V, Disabled 5 µA Bias current at VIN13_SENSE TA = 25°C Bias current measured when VINLDO1S is at 1.2 V 40 µA Source current limit Max current from LDO without exceeding load regulation 1000 mA Sink current limit Max current sinked into LDO without exceeding load regulation (raise output voltage above programmed value to sink current into LDO) 1000 mA |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Korean ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
