PIFE32251B-R68MS datasheet(42/157 Pages) TI1

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TPS650830

SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016

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Specifications

Electrical Characteristics (continued)

Over recommended free-air temperature range and over recommended input voltage range (typical at an ambient

temperature range of 25°C) (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

(1)

All values referred to VIH min and VIH max levels.

VR5_Powergood Mask time during

DVS ramp up (exit DVS)

Powergood is kept high and masked

during DVS exit, ramp up, and until 100

µs after the internal reference has

stepped up to the final voltage setting.

ramp-

up + 90

ramp-

up +

100

ramp-

up +

110

μs

VR5_Force PWM time (deglitch

time) during CCM to DCM

transition

PWM is forced for 16 switching cycles

before PFM is enabled turning off the low-

side power MOSFET. Low-side FET

current during each cycle must fall below

the PFM current comparator valley

threshold. Forced PWM allows a fast

transient response and smaller output

voltage ripple during the transition.

cycles

VR5_Force PWM time during DVS

ramp down (enter DVS)

PWM is forced during DVS enter, ramp

down, and until 10 µs after the internal

reference has stepped down to the final

voltage setting. Forced PWM allows a fast

transient response and smaller output

voltage ripple during the transition.

ramp-

down +

ramp-

down +

ramp-

down +

μs

VR5_Force PWM time during DVS

ramp up (exit DVS)

PWM is forced during DVS exit, ramp up,

and until 10 µs after the internal reference

has stepped up to the final voltage

setting. Forced PWM allows a fast

transient response and smaller output

voltage ripple during the transition.

ramp-

up + 9

ramp-

up + 10

ramp-

up + 11

μs

Overtemperature protection

130

145

160

°C

Overtemperature hysteresis

°C

INPUT POWER SOURCE DETECTION

POWER MONITORING 1-Hz CLOCK - 1-Hz EC CLOCK - pulledup to Internal Pull-up Rail = EC_VCC = 1.8 V or 3.3 V

Clock frequency (1)

0.8

1.2

Duty cycle

50%

VPP

Pull-up output voltage supply

Pulled-Up to EC_VCC pin which should

be tied to 3.3-V LDO3V pin, can also

have EC_VCC pull-up to 1.8 V, instead of

3.3 V.

EC_VC

VOL_PP

Low level output voltage

IOL = 3 mA

0.66

VOH_PP

High level output voltage

IOH = 3 mA

EC_VC

C - 0.66

COINCELL SELECTOR

V3v1LDO

3V1 LDO regulation voltage

VDCIN > UVLO, 3.3-V and 5-V LDOs up,

Measured at the V3P3A_RTC pin with

respect to AGND. Place a 1-µF capacitor

at V3P3A_RTC. (Do not exceed 2 µF

actual capacitance).

3.0

3.1

3.2

I3v1LDO

Maximum 3V1 LDO output current

Maximum output current out of 3V3RTC.

IQ_bkup_no_Vsys

VBATTBKUP quiescent current,

when no adapter and no main

battery connected to system,

automatically VBATTBKUP

internally selected, internal 3.1-V

LDO automatically off

VVDC < UVLO, VBBC = 2.0 V to 3.0 V,

VVDC = 0 V

0.03

0.45

μA

IQ_bkup_with_Vsys

VBATTBKUP quiescent current,

when adapter or main battery

connected to system, automatically

VBATTBKUP internally not

selected, internal 3.1-V LDO

automatically on and selected.

VVDC > UVLO, VBBC = 2.0 V to 3.0 V,

VVDC = 7.4 V

0.15

0.85

μA

PIFE32251B-R68MS 데이터시트(PDF) 42 Page - Texas Instruments

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