PIFE32251B-R68MS datasheet(71/157 Pages) TI1

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TPS650830

www.ti.com

SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016

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Detailed Description

6.4.1

OFF State - No VIN and No Backup Battery

If the VIN and the VBATTBKUP battery are both lower than their respective UVLOs then, the device will

be in the OFF state. In this state the device will not be able to turn on or enable any VRs or discrete load

switches / regulators. The clock and I2C are not active in this state.

In the OFF state, the power path switch comparators, ACIN, BAT1, and BAT2 are the only block available

for use. In order to use these comparators the VINPP must be supplied with the highest of the 3 input

voltages from AC, BAT1, and BAT2. In all other states the VINPP must be supplied from the same source

as VIN.

6.4.2

Startup

The device enters STARTUP once the VIN > UVLO. During STARTUP LDO3V, LDO5V, and VREF1V25

ramp up. Once both LDO3V and LDO5V reach their nominal voltage and their powergoods assert HIGH,

the OTP loads into the I2C registers. After the LDO5V_PG asserts HIGH, the RTC LDO is turned on and

the V3.3A_RTC is regulated to 3.1 V powered from the LDO5V. Once the OTP is loaded and the RTC is

regulated to 3.1 V the device enters READY state.

6.4.3

Ready State

The device is considered to be in the READY state once, all of the internal supplies and RTC are

regulated and the OTP is loaded into the registers. In this state the device is ready for enable commands.

The comparators, level shifters and all other blocks are available for use.

6.4.4

S5/S4 State

The S5/S4 states are entered when the V3.3A_DSW, V1.8A, V5A_DS3, V3.3A_PCH, V0.85A, and V1.00A

are all enabled and regulating with valid powergoods. In this state the RSMRST#_PWRGD will be

asserted HIGH.

6.4.5

S3 State

To enter S3 state the SLP_S4# signal must be asserted HIGH. Upon SLP_S4# assertion the VDDQ

(VR4), and V1.8U rails are turned on.

6.4.6

S0 State

To enter S0 state the SLP_S3# signal must be asserted HIGH in addition to valid 3.3-V, 1.8-V, and 1.0-V

signals on VSE, VSF, and VSG pins. Upon PGG = 1 and PGVR4 = 1 the VCCIO and rail is turned on and

the device transitions to S0 state. ALL_SYS_PWRGD asserts HIGH in this state.

6.4.7

Standby

Standby is entered when the STANDBYZ pin transitions from HIGH to LOW provided that

ALL_SYS_PWRGD is HIGH. During the STANDBY state the device will DVS and/or decay the VRs that

are programmed to DVS or decay from the I2C register definitions, (registers x30 - x38).

6.4.8

DSx State

The DSx state is entered from STARTUP by the enabling of V3.3A_DSW. From the S5/S4 states it can be

entered by either pulling the SLP_SUS# signal LOW or writing to VREN, EC_SLP_S4 = EC_DS4 = 1. In

this state, the V5A_DS3 and V1.8A may be turned off.

6.4.9

Emergency Shutdown

Emergency Shutdown is a protection feature for the system loads. It reduces the risk of reverse bias in the

processor or other devices from once rail to another. Once Emergency Shutdown is initiated the

DPWROK pin is pulled LOW, discharge resistors are enabled for all rails, and all rails are disabled at the

same time. The PMIC remains in Emergency Shutdown until any of the follow occurs:

PIFE32251B-R68MS 데이터시트(PDF) 71 Page - Texas Instruments

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