PIFE32251B-R68MS datasheet(73/157 Pages) TI1

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TPS650830

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SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016

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Detailed Description

The master then generates the SCL pulses, and transmits the 7-bit address and the read/write direction bit

R/W on the SDA line. During all transmissions, the master ensures that data is valid. A valid data

condition requires the SDA line to be stable during the entire high period of the clock pulse, see Figure 6-

18. All devices recognize the address sent by the master and compare it to their internal fixed addresses.

Only the slave device with a matching address generates an acknowledge, see Figure 6-19, by pulling the

SDA line low during the entire high period of the ninth SCL cycle. Upon detecting this acknowledge, the

master knows that the communication link with a slave has been established.

The master generates further SCL cycles to either transmit data to the slave (R/W bit = 0) or receive data

from the slave (R/W bit = 1). In either case, the receiver needs to acknowledge the data sent by the

transmitter. An acknowledge signal can either be generated by the master or by the slave, depending on

which one is the receiver. 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can

continue as long as necessary.

To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from

low to high while the SCL line is high, see Figure 6-17. This releases the bus and stops the

communication link with the addressed slave. All I2C compatible devices must recognize the stop

condition. Upon the receipt of a stop condition, all devices know that the bus is released, and they wait for

a start condition followed by a matching address

Attempting to read data from register addresses not listed in this section results in FFh being read out. FS

I2C operation does not support repeated start

PIFE32251B-R68MS 데이터시트(PDF) 73 Page - Texas Instruments