PIFE32251B-R68MS datasheet(41/157 Pages) TI1

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TPS650830

www.ti.com

SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016

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Specifications

Electrical Characteristics (continued)

Over recommended free-air temperature range and over recommended input voltage range (typical at an ambient

temperature range of 25°C) (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DVS ramp time for rising edge

From first switching pulse to 95% of

VO(Min), Continuous slope (no slope

reversal). Total ramp time = ((Vout_high -

Vout_low) / slew_rate). For Vout change

= 300 mV.

μs

DVS slew rate for rising edge

DVS rising edge slew rate for VVOUT to

change from the lower target to the upper

target after STANDBYZ (SLP_S0#)

changes from Low to High . Total ramp

time = ((Vout_high - Vout_low) /

slew_rate).

4.5

5.5

mV / μs

VR5 Controller MOSFET Drivers

DRVH resistance

Source, IDRVH = -50 mA

3.0

4.5

DRVH resistance

Sink, IDRVH = 50 mA

2.0

3.5

DRVL resistance

Source, IDRVL = -50 mA

3.0

4.5

DRVL resistance

Sink, IDRVL = 50 mA

0.8

2.0

Dead time

DRVH - off to DRVL - on

Dead time

DRVL - off to DRVH - on

High-side driver minimum on-time

DRVH - on

105

High-side driver minimum off-time

DRVH - off

235

260

285

VR5 Controller OUTPUT DISCHARGE

Output auto discharge resistance

Discharge register value: 00, Default

1000

kΩ

Output auto discharge resistance

Discharge register value: 01

150

190

Output auto discharge resistance

Discharge register value: 10

170

250

315

Output auto discharge resistance

Discharge register value: 11

450

575

690

VR5_Controller Feedback input

resistance

Controller enabled

2.5

4.25

MΩ

VR5_Bootstrap switch ON

resistance (Rdson)

TA = 25°C

VR5_Controller HSD leakage

VIN = 7.4 V, Controller disabled

1.55

μA

VR5 Controller CONTROL

VR5_Powergood exit threshold

high

Fail when Vout increasing

105.5%

108%

110.5%

VR5_Powergood threshold high

hysteresis

Good when Vout decreases (after a

PGOOD fail event)

-3%

VR5_Powergood exit threshold low Fail when Vout decreasing

89.5%

92%

94.5%

VR5_Powergood threshold low

hysteresis

Good when Vout increases (after a

PGOOD fail event)

VR5_Powergood deglitch time for

both rising and falling edges

FBVR5P voltage must cross powergood

threshold and stay for at least this time to

change powergood output state.

Measured from FBVR5P into or out of

powergood threshold, until PGVR5

toggles, for both rising and falling edges.

μs

VR5_Powergood Mask time during

and after soft-start ramp-up time

Powergood is kept low and power fault is

masked during soft-start until 100 µs after

the internal reference has stepped up to

the final voltage setting.

VR5_Powergood Mask time during

DVS ramp down (enter DVS)

Powergood is kept high and masked

during DVS enter, ramp down, and until

100 µs after the internal reference has

stepped down to the final voltage setting.

ramp-

down +

ramp-

down +

100

ramp-

down +

110

μs

PIFE32251B-R68MS 데이터시트(PDF) 41 Page - Texas Instruments

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