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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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PIFE32251B-R68MS 데이터시트(PDF) 31 Page - Texas Instruments |
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PIFE32251B-R68MS 데이터시트(HTML) 31 Page - Texas Instruments |
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31 / 157 page  31 TPS650830 www.ti.com SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 Submit Documentation Feedback Product Folder Links: TPS650830 Specifications Copyright © 2014–2016, Texas Instruments Incorporated Electrical Characteristics (continued) Over recommended free-air temperature range and over recommended input voltage range (typical at an ambient temperature range of 25°C) (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DVS ramp time for falling edge From first switching pulse to 5% of VO(Min), Continuous slope (no slope reversal). Total ramp time = ((Vout_high - Vout_low) / slew_rate). For Vout change = 300 mV 55 60 67 μs DVS slew rate for falling edge DVS falling edge slew rate for VVOUT to change from the upper target to the lower target after STANDBYZ (SLP_S0#) changes from High to Low. Total ramp time = ((Vout_high - Vout_low) / slew_rate) 4.5 5 5.5 mV / μs DVS total rise time (delay time + output ramp-rise time) Time to start switching from enable to 95% of VO(Min), Continuous slope (no slope reversal). 56 61.25 68.5 μs DVS delay time for rising edge DVS delay time from when STANDBYZ (SLP_S0#) changes from Low to High, until the output voltage begins to rise. 1 1.25 1.5 μs DVS ramp time for rising edge From first switching pulse to 95% of VO(Min), Continuous slope (no slope reversal). Total ramp time = ((Vout_high - Vout_low) / slew_rate). For Vout change = 300 mV 55 60 67 μs DVS slew rate for rising edge DVS rising edge slew rate for VVOUT to change from the lower target to the upper target after STANDBYZ (SLP_S0#) changes from Low to High. Total ramp time = ((Vout_high - Vout_low) / slew_rate). 4.5 5 5.5 mV / μs Decay exit Total turn-on time (delay time + output ramp-up time) Time to start switching from enable to 95% of VO(Min), Continuous slope (no slope reversal). 66 75 95 μs Decay exit delay time for rising edge Decay delay time from when STANDBYZ (SLP_S0#) changes from Low to High, until the output voltage begins to rise. 10 12 16 μs Decay exit ramp time for rising edge From first switching pulse to 95% of VO(Min), Continuous slope (no slope reversal). Total ramp time = ((Vout_high - 0V) / slew_rate). For Vout target = 0.95. 56 63 79 μs Decay exit slew rate for rising edge Decay rising edge slew rate for VVOUT to change from the lower target to the upper target after STANDBYZ (SLP_S0#) changes from Low to High. Total ramp time = ((Vout_high - 0 V) / slew_rate). 12 15 17 mV / μs VR3 Controller MOSFET Drivers DRVH resistance Source, IDRVH = -50 mA 3.0 4.5 Ω DRVH resistance Sink, IDRVH = 50 mA 2.0 3.5 Ω DRVL resistance Source, IDRVL = -50 mA 3.0 4.5 Ω DRVL resistance Sink, IDRVL = 50 mA 0.8 2.0 Ω Dead time DRVH - off to DRVL - on 10 ns Dead time DRVL - off to DRVH - on 20 ns High-side driver minimum on-time DRVH - on 65 80 105 ns High-side driver minimum off-time DRVH - off 235 260 285 ns VR3 Controller OUTPUT DISCHARGE Output auto discharge resistance Discharge register value: 00, Default 1000 kΩ Output auto discharge resistance Discharge register value: 01 90 125 160 Ω Output auto discharge resistance Discharge register value: 10 170 225 315 Ω |
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