PIFE32251B-R68MS datasheet(62/157 Pages) TI1

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VOUT

Dynamic Voltage Scaling (DVS) Timing

FORCE

PWM

PGOOD

MASK

Number of Steps *T,

where Number of Steps = [(VOUT_hi – VOUT_lo)/25mV per step];

T=3, 5, 6, or 7us per step

100us

10us

100us

10us

Number of Steps *T

STANDBY#

(LPM)

Low Power Mode (LPM)

TPS650830

SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016

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Detailed Description

Figure 6-11. Dynamic Voltage Scaling (DVS) Transition Timing

The DVS Timing is controlled by the stepping the internal reference down/up. The total ramp down/up

transition time is equal to the step time times the number of steps. The number of steps is equal to [(the

VOUT_hi voltage minus the VOUT_lo voltage) divided by 25 mV per step]. The step time of 5 µs per 25-

mV step ensures a time less than 70 µs for a 300-mV voltage change. The Controller is forced in PWM

from the STANDBY# (LPM) transition until 10 µs after the reference ramp down/up ends. This helps

ensure a fast response. Likewise the Powergood signal for that rail is masked from the STANDBY# (LPM)

transition until 100 µs after the internal reference ramp down/up ends. This ensures there is no false

powergood fault turn-off during DVS. In most cases undershoot/overshoot is negligible.

PIFE32251B-R68MS 데이터시트(PDF) 62 Page - Texas Instruments