PIFE32251B-R68MS datasheet(65/157 Pages) TI1

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PFM Mode at Light Load

PFM Ripple

PWM Mode at Heavy Load

Nominal DC Output Voltage

TPS650830

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SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016

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Detailed Description

6.3.13 Converters

The PMIC has 5 built in DCDC converters. The voltage regulators are highly configurable both in terms of

voltage and current. Of the five voltage regulators, four voltage regulators have an external power stage,

with programmable current limit (programmed by an external resistor), which allows optimal selection of

external passive components based on desired system load. VR2 has a completely integrated power

stage, except for the required passive components. To maintain high efficiency, the converters are

implemented as synchronous step down converters.

One additional voltage regulators in the form of Low Drop Out (LDO) linear regulators are integrated as

part of the PMIC. One of the LDOs, LDO1, is capable of sinking and sourcing current that regulates from

the step down controller (for DDR memory). This LDO is designed to specifically provide the VTT power to

DDR memory. Its output voltage tracks the output voltage of the step down controller and is set to regulate

to half of the step down controller voltage.

6.3.13.1 Power Save Mode

At medium and heavy loads, the converter and the controllers operate in a PWM mode. As soon as the

inductor current gets discontinuous, which means that the output current gets lower than half of the

inductor ripple current, the converters enter Power Save Mode. In Power Save Mode the switching

frequency decreases linearly with the load current and maintains a high efficiency. By default, the

converters and controller operate in the AutoPFM mode such that the transition into and out of Power

Save Mode happens within the entire regulation scheme and is seamless in both directions.

Figure 6-14. PFM and PWM Mode Operation

The figure above shows the converter/ controller operation in PFM and PWM mode. In PFM mode the

minimum voltage that the output falls to is the programmed regulation voltage. The output voltage ripple in

PFM mode is determined based on the external passive components (L and C). The regulator ensures

that the minimum voltage during PFM mode is the same as the programmed regulation voltage (within the

AC and DC tolerance).

PIFE32251B-R68MS 데이터시트(PDF) 65 Page - Texas Instruments