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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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PIFE32251B-R68MS 데이터시트(PDF) 25 Page - Texas Instruments |
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PIFE32251B-R68MS 데이터시트(HTML) 25 Page - Texas Instruments |
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25 / 157 page  25 TPS650830 www.ti.com SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 Submit Documentation Feedback Product Folder Links: TPS650830 Specifications Copyright © 2014–2016, Texas Instruments Incorporated Electrical Characteristics (continued) Over recommended free-air temperature range and over recommended input voltage range (typical at an ambient temperature range of 25°C) (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Decay exit slew rate for rising edge Decay rising edge slew rate for VVOUT to change from the lower target to the upper target after STANDBYZ (SLP_S0#) changes from Low to High . Total ramp time = ((Vout_high - 0 V) / slew_rate). 12 15 17 mV / μs VR1 Controller MOSFET Drivers DRVH resistance Source, IDRVH = -50 mA 3.0 4.5 Ω DRVH resistance Sink, IDRVH = 50 mA 2.0 3.5 Ω DRVL resistance Source, IDRVL = -50 mA 3.0 4.5 Ω DRVL resistance Sink, IDRVL = 50 mA 0.8 2.0 Ω Dead time DRVH - off to DRVL - on 10 ns Dead time DRVL - off to DRVH - on 20 ns High-side driver minimum on-time DRVH - on 65 80 105 ns High-side driver minimum off-time DRVH - off 235 260 285 ns VR1 Controller OUTPUT DISCHARGE Output auto discharge resistance Discharge register value: 00, Default 1000 kΩ Output auto discharge resistance Discharge register value: 01 90 125 160 Ω Output auto discharge resistance Discharge register value: 10 170 225 315 Ω Output auto discharge resistance, Default Discharge register value: 11 450 550 690 Ω VR1_Controller Feedback input resistance Controller enabled 1 2.25 MΩ VR1_Bootstrap switch ON resistance (Rdson) -40 ≤ TA ≤ 125°C 15 25 Ω VR1 Controller CONTROL VR1_Powergood exit threshold high Fail when Vout increasing 105.5% 108% 110.5% VR1_Powergood threshold high hysteresis Good when Vout decreases (after a PGOOD fail event) -3% VR1_Powergood exit threshold low Fail when Vout decreasing 89.5% 92% 94.5% VR1_Powergood threshold low hysteresis Good when Vout increases (after a PGOOD fail event) 3% VR1_Powergood deglitch time for both rising and falling edges FBVR1P voltage must cross powergood threshold and stay for at least this time to change powergood output state. Measured from FBVR1P into or out of powergood threshold, until PGVR1 toggles, for both rising and falling edges. 27 30 33 μs VR1_Powergood Mask time during and after soft-start ramp-up time Powergood is kept low and power fault is masked during soft-start until 100 µs after the internal reference has stepped up to the final voltage setting. 9 10 11 ms VR1_Powergood Mask time during DVS ramp down (enter DVS) Powergood is kept high and masked during DVS enter, ramp down, and until 100 µs after the internal reference has stepped down to the final voltage setting. ramp- down + 90 ramp- down + 100 ramp- down + 110 μs VR1_Powergood Mask time during DVS ramp up (exit DVS) Powergood is kept high and masked during DVS exit, ramp up, and until 100 µs after the internal reference has stepped up to the final voltage setting. ramp- up + 90 ramp- up + 100 ramp- up + 110 μs |
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