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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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PIFE32251B-R68MS 데이터시트(PDF) 10 Page - Texas Instruments |
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PIFE32251B-R68MS 데이터시트(HTML) 10 Page - Texas Instruments |
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10 / 157 page  10 TPS650830 SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 www.ti.com Submit Documentation Feedback Product Folder Links: TPS650830 Pin Configuration and Functions Copyright © 2014–2016, Texas Instruments Incorporated Table 4-1. Pin Functions (continued) PIN I/O TYPE(1) DESCRIPTION NAME ZAJ PACKAGE NUMBER ZCG PACKAGE NUMBER ENVR1 M12 R15 I D VR1 Enable ENVR2 F11 J14 I D VR2 Enable ENVR3 E9 D11 I D VR3 Enable ENVR4 C2 B2 I D VR4 Enable ENVR5 M2 R2 I D VR5 Enable EN3V3SW K3 L1 I D Enable for load switch from LDO3V pin to VOUT3V3SW output pin EN5VSW M5 P7 I D Enable Internal load switch from 5-V switching regulator to LDO5V output through VIN5VSW. Connect to powergood of 5-V switching regulator. FBLDO1 D8 F9 I AS LDO1 Feedback voltage kelvin sense, (Connect to vout of LDO1 at output load capacitor) FBVR1N J9 K11 I AS VR1 Negative feedback remote sense (Connect to GND of VR1 at output load capacitor) FBVR1P K10 J10 I AS VR1 Positive feedback remote sense (Connect to vout of VR1 at output load capacitor) FBVR2N E10 G12 I AS VR2 Negative feedback remote sense (Connect to GND of VR2 at output load capacitor) FBVR2P G10 G10 I AS VR2 Positive feedback remote sense (Connect to vout of VR2 at output load capacitor) FBVR3N D7 E8 I AS VR3 Negative feedback remote sense (Connect to GND of VR3 at output load capacitor) FBVR3P C10 F11 I AS VR3 Positive feedback remote sense (Connect to vout of VR3 at output load capacitor) FBVR4N D5 E6 I AS VR4 Negative feedback remote sense (Connect to GND of VR4 at output load capacitor) FBVR4P C3 F5 I AS VR4 Positive feedback remote sense (Connect to vout of VR4 at output load capacitor) FBVR5N L4 H5 I AS VR5 Negative feedback remote sense (Connect to GND of VR5 at output load capacitor) FBVR5P G4 J6 I AS VR5 Positive feedback remote sense (Connect to vout of VR5 at output load capacitor) ILIMVR1 L9 M11 I AS VR1 Current limit setting, low-side FET valley current limit ILIMVR3HS D10 E12 I AS VR3 Current limit setting, high-side FET peak current limit ILIMVR3LS C9 E10 I AS VR3 Current limit setting, low-side FET valley current limit ILIMVR4 D2 F3 I AS VR4 Current limit setting, low-side FET valley current limit ILIMVR5HS K5 M7 I AS VR5 Current limit setting, high-side FET peak current limit ILIMVR5LS L5 N6 I AS VR5 Current limit setting, low-side FET valley current limit LDO3V N8 T10 O AS 3.3-V LDO used as a reference voltage, and as a pull-up supply. LDO5V N7 T9 O AS 5-V internal supply used primarily for the gate drives LVA L12 N14 O D Level shifter A open-drain output, used for BC_ACOK output level shifted to EC_VCC. Input is from ACOK pin LVB L10 N12 O D Level shifter B push-pull output, level shifted to VDDLV. Input is from ENH pin NVDC# H9 K9 I D NVDC select [two-level: Low = NVDC, High = non-NVDC]. Connect NVDC# to GND for NVDC, Connect NVDC# to LDO3V for non-NVDC PCH_PWRBTNZ K2 N2 O D Power button signal to PCH (Open-drain output) (active low) PCH_PWROK E11 G14 O D Core and Non Core powergood, Delayed version of ALL_SYS_PWRGD, (Open-drain output) PGA D6 C12 O D Powergood comparator output, push-pull to VDDPG PGB C5 A10 O D Powergood comparator output, push-pull to VDDPG |
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