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PIFE32251B-R68MS 데이터시트(PDF) 105 Page - Texas Instruments

부품명 PIFE32251B-R68MS
상세설명  Simple and Flexible Wide Input Voltage PMU for Mobile Computers
PDF  157 Pages
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제조업체  TI1 [Texas Instruments]
홈페이지  http://www.ti.com
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PIFE32251B-R68MS 데이터시트(HTML) 105 Page - Texas Instruments

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105
TPS650830
www.ti.com
SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016
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Product Folder Links: TPS650830
Detailed Description
Copyright © 2014–2016, Texas Instruments Incorporated
6.6.1.36 VRENPINMASK Register (address = 0x43) [reset = 00000000]
Figure 6-58. VRENPINMASK Register Format
B7
B6
B5
B4
B3
B2
B1
B0
MV12EN
MV11EN
MV10EN
MV9EN
MV8EN
MV7EN
MV5EN
MV4EN
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-39. VRENPINMASK Register Field Descriptions
Bit
Field
Type
Reset
Description
7
MV12EN
RW
0
V12 Enable Pin Mask
0: VR Enable Pin controls VR enable
1: VR Enable Pin masked V*CTLV controls VR enable
6
MV11EN
RW
0
V11 Enable Pin Mask
0: VR Enable Pin controls VR enable
1: VR Enable Pin masked V*CTLV controls VR enable
5
MV10EN
RW
0
V10 Enable Pin Mask
0: VR Enable Pin controls VR enable
1: VR Enable Pin masked V*CTLV controls VR enable
4
MV9EN
RW
0
V9 Enable Pin Mask
0: VR Enable Pin controls VR enable
1: VR Enable Pin masked V*CTLV controls VR enable
3
MV8EN
RW
0
V8 Enable Pin Mask
0: VR Enable Pin controls VR enable
1: VR Enable Pin masked V*CTLV controls VR enable
2
MV7EN
RW
0
V7 Enable Pin Mask
0: VR Enable Pin controls VR enable
1: VR Enable Pin masked V*CTLV controls VR enable
1
MV5EN
RW
0
V5 Enable Pin Mask
0: VR Enable Pin controls VR enable
1: VR Enable Pin masked V*CTLV controls VR enable
0
MV4EN
RW
0
V4 Enable Pin Mask
0: VR Enable Pin controls VR enable
1: VR Enable Pin masked V*CTLV controls VR enable



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