ADPD4100 datasheet(29/101 Pages) AD

29 / 101 page

Data Sheet

ADPD4100/ADPD4101

Rev. 0 | Page 29 of 101

In continuous connect mode using 2 µs LED pulses, the

automatic period calculation is

Period = (2 + 2 × INTEG_WIDTH_x + (Number of

Channels Enabled × (ADC_COUNT_x + 1)))

The integration pulses are controlled with the INTEG_

OFFSET_x and INTEG_WIDTH_x bits. It is recommended

that an integration width of 1 μs greater than the LED width be

used because the signal spreads due to the response of the BPF.

By setting the integration width 1 μs wider than the LED width,

a maximum amount of charge from the incoming signal is

integrated.

The number of ADC conversions defaults to a single ADC

conversion. However, oversampling is available for increased

SNR. The ADC conversions can be set to 1, 2, 3, or 4, based on

the ADC_COUNT_x bits.

If two channels are enabled, Channel 1 occurs first, followed by

Channel 2.

The total number of pulses is equal to NUM_INT_x × NUM_

REPEAT_x. In continuous connect mode, NUM_INT_x = 1 for

a single integration sequence per ADC conversion. Therefore,

the total number of pulses is controlled by NUM_REPEAT_x.

Increasing the number of pulses reduces the noise floor of the

measurement by a factor of √n, where n is the total number of

pulses.

Figure 35 shows the timing operation where a single integration

cycle is used per ADC conversion. Table 18 details the relevant

registers using continuous connect mode for a PPG measurement.

Table 18. Continuous Connect Mode Settings

Group

Time Slot A Register

Address1

Bit Field Name

Description

Signal Path

Setup

0x0100, Bits[13:12]

SAMPLE_TYPE_x

Leave at the default setting (0) for default sampling mode.

0x0101, Bits[8:0]

AFE_PATH_CFG_x

Set to 0x0DA for TIA, BPF, integrator, and ADC.

0x0102, Bits[15:0]

INPxx_x

Enable desired inputs.

0x0103, Bits[14:12]

PRECON_x

Set to 0x5 to precondition anode of the photodiode to TIA_VREF.

0x0103, Bits[7:6], Bits[1:0]

VCx_SEL_x

Set to 0x2 to set ~215 mV reverse bias across the photodiode.

0x0104, Bits[5:0]

TIA_GAIN_CHx_x

Select TIA gain.

0x0104, Bits[9:8]

AFE_TRIM_VREF_x

Set to 0x3 to set TIA_VREF = 1.27 V for maximum dynamic range.

0x0108, Bits[13:12]

MOD_TYPE_x

Set to 0 for continuous TIA connection to inputs following

preconditioning.

Timing

0x0109, Bits[7:0]

LED_OFFSET_x

Sets start time of first LED pulse in 1 μs increments. 0x10 default

(16 μs).

0x0109, Bits[15:8]

LED_WIDTH_x

Sets width of LED pulse in 1 μs increments. 2 μs recommended.

0x010A, Bits[4:0]

INTEG_WIDTH_x

Integration time in µs. Set to LED_WIDTH_x + 1.

0x010B, Bits[12:0]

INTEG_OFFSET_x

Integration sequence start time = INTEG_OFFSET_x. Optimize as

described in the Optimizing Position of Integration Sequence

section.

0x0107, Bits[15:8]

NUM_INT_x

Set to 1 for a single integration per group of ADC conversions.

0x0107, Bits[7:0]

NUM_REPEAT_x

With NUM_INT_x = 1, NUM_REPEAT_x sets the total number of

pulses.

LED Settings

0x0105, Bit 15 and Bit 7;

0x0106, Bit 15 and Bit 7

LED_DRIVESIDEx_x

Select LED for time slot used.

0x0105, Bits[14:8], Bits[6:0];

0x0106, Bits[14:8], Bits[6:0]

LED_CURRENTx_x

Set LED current for selected LED.

Integrator

Chop Mode2

0x010D, Bits[7:4]

SUBTRACT_x

Four-pulse subtract pattern. Set to 1 to negate the math operation

in the matching position in a group of four pulses. The LSB maps to

the first pulse.

0x010D, Bits[3:0]

REVERSE_INTEG_x

Four-pulse integration reverse pattern. Set to 1 to reverse the

integrator positive and negative pulse order in the matching

position in a group of four pulses. The LSB maps to the first pulse.

This is the Time Slot A register address. Add 0x020 for the identical register address for each subsequent time slot. For example, Register 0x0100 is the location for

SAMPLE_TYPE_A. For Time Slot B, this register is at Address 0x0120. For Time Slot C, this register is at Address 0x0140. For Time Slot D, this register is at

Address 0x0160, and so on.

See the Improving SNR Using Integrator Chopping section for more information about integrator chop mode.

ADPD4100 데이터시트(PDF) 29 Page - Analog Devices

ADPD4100 데이터시트(HTML) 29 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL