ADPD4100 datasheet(84/101 Pages) AD

84 / 101 page

ADPD4100/ADPD4101

Data Sheet

Rev. 0 | Page 84 of 101

CLOCK AND TIMESTAMP SETUP AND CONTROL REGISTERS

Table 33. Clock and Timestamp Setup and Control Register Details

Addr

Name

Bits

Bit Name

Description

Reset Access

0x0009 OSC32M

[15:8]

Reserved

Reserved.

0x0

[7:0]

OSC_32M_FREQ_ADJ

High frequency oscillator frequency control. 0x00 is the lowest

frequency, and 0xFF is maximum frequency.

0x80

R/W

0x000A OSC32M_CAL 15

OSC_32M_CAL_START

Start high frequency oscillator calibration cycle. Writing a 1 to

this bit causes the high frequency oscillator calibration cycle to

occur. 32 MHz oscillator cycles are counted during 128 low

frequency oscillator cycles if using the 1 MHz low frequency

oscillator, or 32 low frequency oscillator cycles if using the

32 kHz low frequency oscillator. The OSC_32M_CAL_COUNT

bits are updated with the count. The calibration circuit clears

the OSC_32M_CAL_START bit when the calibration cycle is

completed.

0x0

R/W

[14:0]

OSC_32M_CAL_COUNT

High frequency oscillator calibration count. These bits contain

the total number of 32 MHz cycles that occurred during the

last high frequency oscillator calibration cycle.

0x0

0x000B OSC1M

[15:11] Reserved

Reserved.

0x0

CLK_CAL_ENA

Enables clock for oscillator calibration. When set to 0 (default),

the oscillator calibration circuitry is disabled. Set this bit to 1 to

turn on the oscillator calibration circuitry.

0x0

R/W

[9:0]

OSC_1M_FREQ_ADJ

Low frequency oscillator frequency control. 0x000 is the lowest

frequency, and 0x3FF is maximum frequency.

0x2B2 R/W

0x000C OSC32K

CAPTURE_TIMESTAMP

Enable time stamp capture. This bit is used to activate the time

stamp capture function. When set, the next rising edge on the

time stamp input (defaults to GPIO0) causes a time stamp

capture. This bit is cleared when the time stamp occurs.

0x0

R/W

[14:6]

Reserved

Reserved.

0x0

[5:0]

OSC_32K_ADJUST

32 kHz oscillator trim.

0x12

R/W

00 0000: maximum frequency.

01 0010: default frequency.

11 1111: minimum frequency.

0x0011 STAMP_L

[15:0]

TIMESTAMP_COUNT_L

Count at last time stamp. Lower 16 bits.

0x0

0x0012 STAMP_H

[15:0]

TIMESTAMP_COUNT_H

Count at last time stamp. Upper 16 bits.

0x0

0x0013 STAMPDELTA [15:0]

TIMESTAMP_SLOT_DELTA Count remaining until next time slot start.

0x0

SYSTEM REGISTERS

Table 34. System Register Details

Addr

Name

Bits

Bit Name

Description

Reset Access

0x0008 CHIP_ID

[15:8]

Version

Mask version.

0x2

[7:0]

CHIP_ID

Chip ID.

0xC2 R

0x002E DATA_HOLD_FLAG [15:12] Reserved

Reserved.

0x0

HOLD_REGS_L

Prevent update of Time Slot L data registers.

0x0

R/W

0: allow data register update.

1: hold current contents of data register.

HOLD_REGS_K

Prevent update of time Slot K data registers.

0x0

R/W

0: allow data register update.

1: hold current contents of data register.

HOLD_REGS_J

Prevent update of Time Slot J data registers.

0x0

R/W

0: allow data register update.

1: hold current contents of data register.

HOLD_REGS_I

Prevent update of Time Slot I data registers.

0x0

R/W

0: allow data register update.

1: hold current contents of data register.

ADPD4100 데이터시트(PDF) 84 Page - Analog Devices

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