ADPD4100 datasheet(41/101 Pages) AD

41 / 101 page

Data Sheet

ADPD4100/ADPD4101

Rev. 0 | Page 41 of 101

Table 24. Relevant Settings for Digital Integration Modes

Group

Time Slot A

Bit Field Name

Description

Signal Path

Setup

0x0100, Bits[13:12]

SAMPLE_TYPE_x

Set to 0x1 for one-region digital integration mode. Set to 0x2 for

two-region digital integration mode.

0x0101, Bits[8:0]

AFE_PATH_CFG_x

Set to 0x0E6 for TIA, integrator, and ADC. Bypass BPF. Integrator

is automatically configured as a buffer when one-region or two-

region digital integration mode is selected.

0x0102, Bits[15:0]

INPxx_x

Enable desired inputs.

0x0103, Bits[14:12]

PRECON_x

Set to 0x5 to precondition anode of photodiode to TIA_VREF.

0x0103, Bits[7:6], Bits[1:0]

VCx_SELECT_x

Set to 0x2 to set ~215 mV reverse bias across photodiode.

0x0104, Bits[5:0]

TIA_GAIN_CHx_x

Select TIA gain.

0x0104, Bits[9:8]

AFE_TRIM_VREF_x

Set to 0x3 to set TIA_VREF = 1.265 V.

0x0104, Bits[12:11]

CH1_TRIM_INT_x

Set to 0x0 or 0x1 to set buffer gain = 1.

0x010A, Bit 11

AFE_INT_C_BUF_x

Set to 1 to convert integrator to buffer.

0x010A, Bits[10:8]

CH1_AMP_DISABLE_x

Set 0x010A, Bit 9 to 1 to power down BPF.

Timing

0x0107, Bits[15:8]

NUM_INT_x

Set to the number of desired ADC conversions in the dark and lit

regions.

0x0107, Bits[7:0]

NUM_REPEAT_x

Number of sequence repeats.

0x0108, Bits[9:0]

MIN_PERIOD_x

Set the period. Automatic period calculation is not supported in

digital integration mode.

0x0113, Bits[8:0]

LIT_OFFSET_x

Set to the time of the first ADC conversion in the lit region.

0x0114, Bits[6:0]

DARK1_OFFSET_x

Set to the time of the first ADC conversion in the Dark 1 region.

0x0114, Bits[15:7]

DARK2_OFFSET_x

Set to the time of the first ADC conversion in the Dark 2 region.

Only used in two-region digital integration mode.

LED Settings

0x0105, Bit 15 and Bit 7;

0x0106, Bit 15 and Bit 7

LED_DRIVESIDEx_x

Select LED for time slot used.

0x0105, Bits[14:8], Bits[6:0];

0x0106, Bits[14:8], Bits[6:0]

LED_CURRENTx_x

Set LED current for selected LED.

0x0109, Bits[7:0]

LED_OFFSET_x

Sets start time of first LED pulse in 1 μs increments.

0x0109, Bits[15:8]

LED_WIDTH_x

Sets width of LED pulse in 1 μs increments.

This is the Time Slot A register address. Add 0x020 for the identical register address for each subsequent time slot. For example, Register 0x0100 is the location for

SAMPLE_TYPE_A. For Time Slot B, this register is at Address 0x0120. For Time Slot C, this register is at Address 0x0140. For Time Slot D, this register is at

Address 0x0160, and so on.

Timing Recommendations for Digital Integration Modes

When setting the timing for digital integration mode, it is

important to place the ADC samples such that the signal being

sampled is given time to settle prior to the sample being taken.

Settling time of the input signal is affected by photodiode

capacitance and TIA settling time. Figure 48 shows an example

of proper placement of the ADC sampling edges. Calculations

for the offset values are as follows:

DARK1_OFFSET_x = (LED_OFFSET_x – (NUM_INT_x + 2))

Add a value of 2 to the number of ADC conversions such that

there is 2 μs of margin added to placement of the Dark 1 region

samples with respect to the beginning of the LED pulse.

LIT_OFFSET_x = (LED_OFFSET_x + tD)

where tD is the delay built into the offset setting to allow settling

time of the signal. This value must be characterized in the final

application. A value in the range of 3 µs to 5 µs is typically

recommended as the tD value.

DARK2_OFFSET_x = (LED_OFFSET_x + LED_WIDTH_x + tD)

This setting only applies to two-region digital integration mode.

TIA

OUTPUT

LED

OUTPUT

ADC

SAMPLES

LED_OFFSET_x

LED_WIDTH_x

DARK1_OFFSET_x

LIT_OFFSET_x

DARK2_OFFSET_x

Figure 48. Proper Placement of ADC Sampling Edges in Digital Integration Mode

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