ADPD4100 datasheet(45/101 Pages) AD

45 / 101 page

Data Sheet

ADPD4100/ADPD4101

Rev. 0 | Page 45 of 101

Table 27. Relevant Configuration Registers for ECG Measurement Using Sleep Float Mode

Group

Time Slot A

Bit Field Name

Description

Signal Path Setup

0x0100, Bits[13:12]

SAMPLE_TYPE_x

Leave at the default setting (0) for default sampling mode.

0x0100, Bits[11:10]

INPUT_R_SELECT_x

Set to 0x0 for 500 Ω series input resistor.

0x0101, Bits[8:0]

AFE_PATH_CFG_x

Set to 0x0E6 for TIA, integrator, and ADC. Bypass the BPF.

0x0101, Bits[15:12]

PRE_WIDTH_x

Set to 0 to skip preconditioning period.

0x0102, Bits[15:0]

INPxx_x

Set to 0x7 to enable desired inputs connected to Channel 1 as defined

in PAIRxx.

0x0103, Bits[4:12]

PRECON_x

Set to 0x0 to float the inputs during preconditioning.

0x0020, Bits[15:0]

INP_SLEEP_xx

Set to 0x0 to float inputs during sleep.

0x0021, Bits[3:0]

PAIRxx

Set to 1 to configure selected inputs as a differential pair.

0x0104, Bits[5:0]

TIA_GAIN_CHx_x

Select TIA gain.

0x0104, Bits[9:8]

AFE_TRIM_VREF_x

Set to 0x2 to set TIA_VREF = 0.9 V.

Float Mode

Configuration

0x0107, Bits[15:8]

NUM_INT_x

Set to 1 for a single integration per group of ADC conversions.

0x0107, Bits[7:0]

NUM_REPEAT_x

Number of sequence repeats.

0x0108, Bits[13:12]

MOD_TYPE_x

Set to 0x1 for float type operation.

0x0108, Bits[9:0]

MIN_PERIOD_x

Set to 0. Minimum period is not applicable to sleep float mode with a

single integration.

0x010A, Bits[4:0]

INTEG_WIDTH_x

Integration time in µs. Set to MOD_WIDTH_x + 1.

0x010A, Bits[10:8],

Bits[14:12]

CHx_AMP_DISABLE_x

Set 0x010A, Bit 9 to 1 to power down BPF for Channel 1, Bit 13 to 1 to

power down BPF for Channel 2 if Channel 2 is enabled.

0x010B, Bits[12:0]

INTEG_OFFSET_x

Integration sequence start time. Set to (MOD_OFFSET_x −

INTEG_WIDTH_x – 250 ns).

0x010C, Bits[15:8]

MOD_WIDTH_x

Sets width of connect pulse in 1 μs increments. MOD_WIDTH_x ×

NUM_REPEAT_x determines the time to transfer the charge from the

external capacitor. Set MOD_WIDTH_x × NUM_REPEAT_x to

approximately three time constants based on the time constant created

between the external capacitor and the series input resistor (500 Ω or

6500 Ω based on setting of INPUT_R_SELECT_x).

0x010C, Bits[7:0]

MOD_OFFSET_x

Sets start time of first connect pulse in 1 μs increments. Set to

INTEG_WIDTH_x + 3.

This is the Time Slot A register address. Add 0x020 for the identical register address for each subsequent time slot. For example, Register 0x0100 is the location for

SAMPLE_TYPE_A. For Time Slot B, this register is at Address 0x0120. For Time Slot C, this register is at Address 0x0140. For Time Slot D, this register is at

Address 0x0160, and so on.

Sleep Float Mode with Multiple Charge Transfers

In ECG measurement, there can be a dc offset voltage on the

order of tens or hundreds of millivolts or even greater when the

electrode skin contact impedance is high and/or the electrodes

are made of different materials with large half cell potential

mismatch. The dc offset voltage uses a significant amount of the

dynamic range available for the ECG measurement. The

maximum amount of charge that the ADPD4100/ADPD4101

can accommodate for a single sample is ~7.5 pC with the

200 kΩ TIA gain setting. The maximum allowable charge per

sample scales inversely with the gain of the TIA. The presence

of a large dc offset voltage creates excess charge on the sensing

capacitor, which can saturate the input to the ADC. For

example, 100 mV of dc offset voltage adds an additional 47 pC

of charge to the 470 pF capacitor.

To accommodate the dc offset voltage without reducing the size

of the sensing capacitor, the recommendation is to reduce the

TIA gain to 50 kΩ or 100 kΩ, and to transfer the accumulated

charge in multiple short pulses. For example, to transfer 47 pC

of charge from the sensing capacitor to the integrator, the TIA

gain of 50 kΩ can accommodate 30 pC of charge per sample.

Setting RIN = 6.5 kΩ limits the rate of charge transfer into the

TIA with an RC time constant of 2 × 6.5 kΩ × 470 pF = 6.1 μs.

Using multiple short modulation pulses, which can be as short

as 1 µs, allows a smaller percentage of the overall charge to be

transferred and integrated per pulse to avoid saturating the TIA.

Multiple transfer cycles are then used to fully discharge the

sensing capacitor. The ADPD4100/ADPD4101 automatically

sum the results of the transfer cycles and report the total charge.

The timing for this mode is the same as shown in Figure 53

except the device is set up for multiple modulation pulses.

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