ADPD4100 datasheet(73/101 Pages) AD

73 / 101 page

Data Sheet

ADPD4100/ADPD4101

Rev. 0 | Page 73 of 101

Addr

Name

Bits

Bit Name

Description

Reset Access1

INT_DATA_K

Time Slot K data register interrupt status. This bit is set

every time the Time Slot K data registers get updated.

Write 1 to this bit to clear the interrupt. The interrupt is

cleared automatically when the Time Slot K data registers

are read if the INT_ACLEAR_DATA_K bit is set.

0x0

R/W1C

INT_DATA_J

Time Slot J data register interrupt status. This bit is set

every time the Time Slot J data registers are updated.

Write 1 to this bit to clear the interrupt. The interrupt is

cleared automatically when the Time Slot J data registers

are read if the INT_ACLEAR_DATA_J bit is set.

0x0

R/W1C

INT_DATA_I

Time Slot I data register interrupt status. This bit is set

every time the Time Slot I data registers are updated.

Write 1 to this bit to clear the interrupt. The interrupt is

cleared automatically when the Time Slot I data registers

are read if the INT_ACLEAR_DATA_I bit is set.

0x0

R/W1C

INT_DATA_H

Time Slot H data register interrupt status. This bit is set

every time the Time Slot H data registers are updated.

Write 1 to this bit to clear the interrupt. The interrupt is

cleared automatically when the Time Slot H data registers

are read if the INT_ACLEAR_DATA_H bit is set.

0x0

R/W1C

INT_DATA_G

Time Slot G data register interrupt status. This bit is set

every time the Time Slot G data registers are updated.

Write 1 to this bit to clear the interrupt. The interrupt is

cleared automatically when the Time Slot G data registers

are read if the INT_ACLEAR_DATA_G bit is set.

0x0

R/W1C

INT_DATA_F

Time Slot F data register interrupt status. This bit is set

every time the Time Slot F data registers are updated.

Write 1 to this bit to clear the interrupt. The interrupt is

cleared automatically when the Time Slot F data registers

are read if the INT_ACLEAR_DATA_F bit is set.

0x0

R/W1C

INT_DATA_E

Time Slot E data register interrupt status. This bit is set

every time the Time Slot E data registers are updated.

Write 1 to this bit to clear the interrupt. The interrupt is

cleared automatically when the Time Slot E data registers

are read if the INT_ACLEAR_DATA_E bit is set.

0x0

R/W1C

INT_DATA_D

Time Slot D data register interrupt status. This bit is set

every time the Time Slot D data registers are updated.

Write 1 to this bit to clear the interrupt. The interrupt is

cleared automatically when the Time Slot D data registers

are read if the INT_ACLEAR_DATA_D bit is set.

0x0

R/W1C

INT_DATA_C

Time Slot C data register interrupt status. This bit is set

every time the Time Slot C data registers are updated.

Write 1 to this bit to clear the interrupt. The interrupt is

cleared automatically when the Time Slot C data registers

are read if the INT_ACLEAR_DATA_C bit is set.

0x0

R/W1C

INT_DATA_B

Time Slot B data register interrupt status. This bit is set

every time the Time Slot B data registers are updated.

Write 1 to this bit to clear the interrupt. The interrupt is

cleared automatically when the Time Slot B data registers

are read if the INT_ACLEAR_DATA_B bit is set.

0x0

R/W1C

INT_DATA_A

Time Slot A data register interrupt status. This bit is set

every time the Time Slot A data registers are updated.

Write 1 to this bit to clear the interrupt. The interrupt is

cleared automatically when the Time Slot A data registers

are read if the INT_ACLEAR_DATA_A bit is set.

0x0

R/W1C

ADPD4100 데이터시트(PDF) 73 Page - Analog Devices

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