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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ADPD4100 데이터시트(PDF) 52 Page - Analog Devices |
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ADPD4100 데이터시트(HTML) 52 Page - Analog Devices |
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52 / 101 page  ADPD4100/ADPD4101 Data Sheet Rev. 0 | Page 52 of 101 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Reg Name Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset R/W 0x0012 STAMP_H [15:8] TIMESTAMP_COUNT_H[15:8] 0x0000 R [7:0] TIMESTAMP_COUNT_H[7:0] 0x0013 STAMPDELTA [15:8] TIMESTAMP_SLOT_DELTA[15:8] 0x0000 R [7:0] TIMESTAMP_SLOT_DELTA[7:0] 0x0014 INT_ENABLE_ XD [15:8] INTX_EN_ FIFO_TH INTX_EN_ FIFO_ UFLOW INTX_EN_ FIFO_ OFLOW Reserved INTX_EN_ DATA_L INTX_EN_ DATA_K INTX_EN_ DATA_J INTX_EN_ DATA_I 0x0000 R/W [7:0] INTX_EN_ DATA_H INTX_EN_ DATA_G INTX_EN_ DATA_F INTX_EN_ DATA_E INTX_EN_ DATA_D INTX_EN_ DATA_C INTX_EN_ DATA_B INTX_EN_ DATA_A 0x0015 INT_ENABLE_ YD [15:8] INTY_EN_ FIFO_TH INTY_EN_ FIFO_ UFLOW INTY_EN_ FIFO_ OFLOW Reserved INTY_EN_ DATA_L INTY_EN_ DATA_K INTY_EN_ DATA_J INTY_ EN_ DATA_I 0x0000 R/W [7:0] INTY_EN_ DATA_H INTY_EN_ DATA_G INTY_EN_ DATA_F INTY_EN_ DATA_E INTY_EN_ DATA_D INTY_EN_ DATA_C INTY_EN_ DATA_B INTY_EN_ DATA_A 0x0016 INT_ENABLE_ XL0 [15:8] Reserved INTX_EN_ LEV0_L INTX_EN_ LEV0_K INTX_EN_ LEV0_J INTX_EN_ LEV0_I 0x0000 R/W [7:0] INTX_EN_ LEV0_H INTX_EN_ LEV0_G INTX_EN_ LEV0_F INTX_EN_ LEV0_E INTX_EN_ LEV0_D INTX_EN_ LEV0_C INTX_EN_ LEV0_B INTX_EN_ LEV0_A 0x0017 INT_ENABLE_ XL1 [15:8] Reserved INTX_EN_ LEV1_L INTX_EN_ LEV1_K INTX_EN_ LEV1_J INTX_EN_ LEV1_I 0x0000 R/W [7:0] INTX_EN_ LEV1_H INTX_EN_ LEV1_G INTX_EN_ LEV1_F INTX_EN_ LEV1_E INTX_EN_ LEV1_D INTX_EN_ LEV1_C INTX_EN_ LEV1_B INTX_EN_ LEV1_A 0x0018 INT_ENABLE_ XT1 [15:8] Reserved INTX_EN_ TCLN1_L INTX_EN_ TCLN1_K INTX_EN_ TCLN1_J INTX_EN_ TCLN1_I 0x0000 R/W [7:0] INTX_EN_ TCLN1_H INTX_EN_ TCLN1_G INTX_EN_ TCLN1_F INTX_EN_ TCLN1_E INTX_EN_ TCLN1_D INTX_EN_ TCLN1_C INTX_EN_ TCLN1_B INTX_EN_ TCLN1_A 0x0019 INT_ENABLE_ XT2 [15:8] Reserved INTX_EN_ TCLN2_L INTX_EN_ TCLN2_K INTX_EN_ TCLN2_J INTX_EN_ TCLN2_I 0x0000 R/W [7:0] INTX_EN_ TCLN2_H INTX_EN_ TCLN2_G INTX_EN_ TCLN2_F INTX_EN_ TCLN2_E INTX_EN_ TCLN2_D INTX_EN_ TCLN2_C INTX_EN_ TCLN2_B INTX_EN_ TCLN2_A 0x001A INT_ENABLE_ YL0 [15:8] Reserved INTY_EN_ LEV0_L INTY_EN_ LEV0_K INTY_EN_ LEV0_J INTY_EN_ LEV0_I 0x0000 R/W [7:0] INTY_EN_ LEV0_H INTY_EN_ LEV0_G INTY_EN_ LEV0_F INTY_EN_ LEV0_E INTY_EN_ LEV0_D INTY_EN_ LEV0_C INTY_EN_ LEV0_B INTY_EN_ LEV0_A 0x001B INT_ENABLE_ YL1 [15:8] Reserved INTY_EN_ LEV1_L INTY_EN_ LEV1_K INTY_EN_ LEV1_J INTY_EN_ LEV1_I 0x0000 R/W [7:0] INTY_EN_ LEV1_H INTY_EN_ LEV1_G INTY_EN_ LEV1_F INTY_EN_ LEV1_E INTY_EN_ LEV1_D INTY_EN_ LEV1_C INTY_EN_ LEV1_B INTY_EN_ LEV1_A 0x001C INT_ENABLE_ YT1 [15:8] Reserved INTY_EN_ TCLN1_L INTY _EN_ TCLN1_K INTY _EN_ TCLN1_J INTY _EN_ TCLN1_I 0x0000 R/W [7:0] INTY _EN_ TCLN1_H INTY _EN_ TCLN1_G INTY_EN_ TCLN1_F INTY_EN_ TCLN1_E INTY_EN_ TCLN1_D INTY_EN_ TCLN1_C INTY_EN_ TCLN1_B INTY_EN_ TCLN1_A 0x001D INT_ENABLE_ YT2 [15:8] Reserved INTY_EN_ TCLN2_L INTY_EN_ TCLN2_K INTY_EN_ TCLN2_J INTY_EN_ TCLN2_I 0x0000 R/W [7:0] INTY_EN_ TCLN2_H INTY_EN_ TCLN2_G INTY_EN_ TCLN2_F INTY_EN_ TCLN2_E INTY_EN_ TCLN2_D INTY_EN_ TCLN2_C INTY_EN_ TCLN2_B INTY_EN_ TCLN2_A 0x001E FIFO_ STATUS_ BYTES [15:8] Reserved ENA_ STAT_TCX 0x0000 R/W [7:0] ENA_ STAT_TC2 ENA_ STAT_TC1 ENA_ STAT_LX ENA_ STAT_L1 ENA_ STAT_L0 ENA_ STAT_D2 ENA_ STAT_D1 ENA_ STAT_ SUM 0x0020 INPUT_SLEEP [15:8] INP_SLEEP_78[3:0] INP_SLEEP_56[3:0] 0x0000 R/W [7:0] INP_SLEEP_34[3:0] INP_SLEEP_12[3:0] 0x0021 INPUT_CFG [15:8] Reserved 0x0000 R/W [7:0] VC2_SLEEP[1:0] VC1_SLEEP[1:0] PAIR78 PAIR56 PAIR34 PAIR12 0x0022 GPIO_CFG [15:8] GPIO_SLEW[1:0] GPIO_DRV[1:0] GPIO_PIN_CFG3[2:0] GPIO_PIN_ CFG2[2] 0x0000 R/W [7:0] GPIO_PIN_CFG2[1:0] GPIO_PIN_CFG1[2:0] GPIO_PIN_CFG0[2:0] 0x0023 GPIO01 [15:8] Reserved GPIOOUT1[6:0] 0x0000 R/W [7:0] Reserved GPIOOUT0[6:0] |
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