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ADPD4100 데이터시트(PDF) 6 Page - Analog Devices |
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ADPD4100 데이터시트(HTML) 6 Page - Analog Devices |
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6 / 101 page ![]() ADPD4100/ADPD4101 Data Sheet Rev. 0 | Page 6 of 101 DIGITAL SPECIFICATIONS IOVDD = 1.7 V to 3.6 V, unless otherwise noted. Table 5. Digital Specifications Parameter Symbol Test Conditions/Comments Min Typ Max Unit LOGIC INPUTS Input Voltage Level SCL, SDA High VIH 0.7 × IOVDD 3.6 V Low VIL −0.3 +0.3 × IOVDD V GPIOx, MISO, MOSI, SCLK, CS High VIH 0.7 × IOVDD IOVDD + 0.3 V Low VIL −0.3 +0.3 × IOVDD V Input Current Level All logic inputs High IIH 10 µA Low IIL −10 µA Input Capacitance CIN 2 pF LOGIC OUTPUTS Output Voltage Level GPIOx, MISO High VOH 2 mA high level output current IOVDD – 0.5 V Low VOL 2 mA low level output current 0.5 V SDA Low VOL1 3 mA low level output current 0.4 V Output Current Level SDA Low IOL VOL1 = 0.4 V 20 mA TIMING SPECIFICATIONS Table 6. I2C Timing Specifications for the ADPD4101 Parameter Symbol Test Conditions/Comments Min Typ Max Unit TIMING REQUIREMENTS See Figure 2 I2C Port1 SCL Frequency 1 Mbps Minimum Pulse Width High t1 260 ns Low t2 500 ns Start Condition Hold Time t3 260 ns Setup Time t4 260 ns SDA Hold Time2 t5 0 Setup Time t6 50 ns SCL and SDA Rise Time t7 120 ns Fall Time t8 120 ns Stop Condition Setup Time t9 260 ns 1 Guaranteed by design. 2 Both timing requirement and switching characteristic. |
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