ADPD4100 datasheet(25/101 Pages) AD

25 / 101 page

Data Sheet

ADPD4100/ADPD4101

Rev. 0 | Page 25 of 101

Optional Status Bytes

There is an option to append each data packet with status bits. This

option is useful for hosts that cannot spare an interrupt channel

to service. The status bytes can each be individually selected in

the FIFO_STATUS_BYTES register. Each bit in the FIFO_

STATUS_BYTES register enables a status byte that is appended

to the data packet in the FIFO. If any bit in the FIFO_STATUS_

BYTES register is set to 1, the byte that is appended to the data

packet contains the status bits, as shown in Table 16. Table 16

shows the order, enable bit, and contents of each status byte.

The 4-bit sequence number cycles from 0 to 15 and is

incremented with a wraparound every time the time slot

sequence completes. This sequence number can also be made

available bitwise on the GPIOx pins.

Interrupt Outputs, Interrupt X and Interrupt Y

The ADPD4100/ADPD4101 support two separate interrupt

outputs, Interrupt X and Interrupt Y. Each interrupt has the option

to be driven to any of the four GPIOx pins. The two different

interrupt outputs can be generated for a host processor if desired.

For example, the FIFO threshold interrupt, INT_FIFO_TH, can

be routed to Interrupt X and used to drive the direct memory

access (DMA) channel of the host, while the INT_FIFO_OFLOW

and INT_FIFO_UFLOW interrupts can be routed to Interrupt

Y and used to drive an additional host interrupt pin. Another

example case includes routing the data interrupt from a single

time slot to Interrupt X and the FIFO threshold interrupt to

Interrupt Y. The host receives one interrupt when the interrupt

of that particular channel occurs and the host can then read

that register directly. Interrupt Y, in this case, is handled by the

host with DMA or with an interrupt. Each of the different

interrupt status bits can be routed to Interrupt X or Interrupt Y,

or both.

For each interrupt, there is an associated Interrupt X and

Interrupt Y enable bit. See Table 31 for a full list of available

interrupts that can be brought out on Interrupt X and Interrupt Y.

The logic for the Interrupt X and Interrupt Y function is a logic

AND of the status bit with its matching enable bit. All enabled

status bits are then logically OR’ed to create the interrupt

function. The enable bits do not affect the status bits.

General-Purpose I/Os

The ADPD4100/ADPD4101 provide four general-purpose I/O

pins: GPIO0, GPIO1, GPIO2, and GPIO3. These GPIOs can be

used as previously described in the Interrupt Outputs, Interrupt

X and Interrupt Y section for interrupt outputs or for providing

external clock signals to the device. The GPIOs can also be used

for many different control signals, as synchronization controls

to external devices, as well as test signals that are useful during

system debugging. All of the available signals that can be

brought out on a GPIOx pin are listed in Table 35.

IOVDD Supply Voltage Consideration

The ADPD4100/ADPD4101 can operate with IOVDD as low as

1.7 V and as high as 3.6 V. LOW_IOVDD_EN in Register 0x00B4

is set to 0x1 for IOVDD lower than 3 V. 0x1 is the default value

for this bit because the typical IOVDD value is 1.8 V.

If 3 V or higher is supplied for IOVDD, the LOW_IOVDD_EN

bit must be set to 0x0 for proper operation.

Table 16. FIFO Status Byte Order and Contents

Byte Order

Enable Bit

Contents1

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ENA_STAT_SUM

Any LEV1_x

Any LEV0_x

4-bit sequence

ENA_STAT_D1

DATA_H

DATA_G

DATA_F

DATA_E

DATA_D

DATA_C

DATA_B

DATA_A

ENA_STAT_D2

DATA_L

DATA_K

DATA_J

DATA_I

ENA_STAT_L0

LEV0_H

LEV0_G

LEV0_F

LEV0_E

LEV0_D

LEV0_C

LEV0_B

LEV0_A

ENA_STAT_L1

LEV1_H

LEV1_G

LEV1_F

LEV1_E

LEV1_D

LEV1_C

LEV1_B

LEV1_A

ENA_STAT_LX

LEV1_L

LEV1_K

LEV1_J

LEV1_I

LEV0_L

LEV0_K

LEV0_J

LEV0_I

ENA_STAT_TC12

TCLN1_H

TCLN1_G

TCLN1_F

TCLN1_E

TCLN1_D

TCLN1_C

TCLN1_B

TCLN1_A

ENA_STAT_TC22

TCLN2_H

TCLN2_G

TCLN2_F

TCLN2_E

TCLN2_D

TCLN2_C

TCLN2_B

TCLN2_A

ENA_STAT_TCX2

TCLN2_L

TCLN2_K

TCLN2_J

TCLN2_I

TCLN1_L

TCLN1_K

TCLN1_J

TCLN1_I

DATA_x refers to the data register interrupts for the corresponding time slot. LEV0_x and LEV1_x refer to Level 0 and Level 1 time slot interrupts, respectively, for

Time Slot A through Time Slot L.

These status bytes are associated with TIA ceiling detection. See the Protecting Against TIA Saturation with TIA Ceiling Detection section for more information.

ADPD4100 데이터시트(PDF) 25 Page - Analog Devices

ADPD4100 데이터시트(HTML) 25 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL