ADPD4100 datasheet(22/101 Pages) AD

22 / 101 page

ADPD4100/ADPD4101

Data Sheet

Rev. 0 | Page 22 of 101

TIME STAMP OPERATION

The time stamp feature is useful for calibration of the low fre-

quency oscillator as well as providing the host with timing

information during time slot operation. Timestamping is sup-

ported by the use of any GPIO as a time stamp request input,

the CAPTURE_TIMESTAMP bit to enable capture of the time

stamp trigger, a time counter running in the low frequency

oscillator domain, and two output registers. The output bits include

TIMESTAMP_COUNT_x, which holds the number of low

frequency oscillator cycles between time stamp triggers, and

TIMESTAMP_SLOT_DELTA, which holds the number of low

frequency oscillator cycles remaining to the next time slot start.

The setup for using the time stamp operation is as follows:

1. Set CLK_CAL_ENA = 1 to enable the oscillator calibration

circuitry.

2. Configure a GPIO to support the time stamp input using the

appropriate GPIO_PIN_CFGx bits. Select the matching

GPIOx to provide the time stamp using the TIMESTAMP_

GPIO bits.

3. Configure the ADPD4100/ADPD4101 for operation and

enable the low frequency oscillator.

4. If the TIMESTAMP_SLOT_DELTA function is desired,

start the time slot operation by placing the device in go

mode using the OP_MODE bit (see Table 15). For low

frequency oscillator calibration, it is only required that the

low frequency oscillator be enabled. The device does not

have to be in go mode for low frequency oscillator

calibration.

Use the following procedure to capture the time stamp:

1. Set the CAPTURE_TIMESTAMP bit to 1 to enable the

capture of the time stamp on the next rising edge of the

selected GPIOx input.

2. The host provides the initial time stamp trigger on the

selected GPIOx at an appropriate time.

3. The CAPTURE_TIMESTAMP bit is cleared when the

time stamp signal is captured unless the TIMESTAMP_

ALWAYS_EN bit is set, in which case, the capture of the

time stamp is always enabled. Reenable the capture if

necessary.

4. The host provides a subsequent time stamp trigger on the

selected GPIO at an appropriate time.

5. The number of low frequency oscillator cycles that

occurred between time stamp triggers can be read from the

TIMESTAMP_COUNT_x bits.

The host must continue to handle the FIFO and/or data register

data normally during time stamp processing.

If using a dedicated pin for a time stamp that does not have

transitions other than the time stamp, set the TIMESTAMP_

ALWAYS_EN bit to avoid automatic clearing of the CAPTURE_

TIMESTAMP bit. This setting removes the need to enable the

time stamp capture each time.

The time stamp can calibrate the low frequency oscillator as

described in the Low Frequency Oscillator Calibration section.

The host can also use TIMESTAMP_SLOT_DELTA to determine

when the next time slot occurs. TIMESTAMP_SLOT_DELTA

can determine the arrival time of the samples currently in the

FIFO. TIMESTAMP_SLOT_DELTA does not account for the

decimation factor.

The time stamp trigger is edge sensitive and can be set to either

trigger on the rising edge (default) or falling edge using

TIMESTAMP_INV.

LOW FREQUENCY OSCILLATOR CALIBRATION

The time stamp circuitry can calibrate either the 32 kHz or

1 MHz low frequency oscillator circuit by adjusting the

frequency to match the timing of the time stamp triggers.

Simply compare the TIMESTAMP_COUNT_x value in low

frequency oscillator cycles to the actual time stamp trigger

period and adjust the OSC_32K_ADJUST or OSC_1M_FREQ_

ADJ value accordingly.

HIGH FREQUENCY OSCILLATOR CALIBRATION

The high frequency oscillator is calibrated by comparing

multiples of its cycles with multiple cycles of the low frequency

oscillator, which is calibrated to the system time. Calibration of

the low frequency oscillator precedes calibration of the high

frequency oscillator. The method for calibrating the high

frequency oscillator is as follows:

1. Set CLK_CAL_ENA = 1 to enable the oscillator calibration

circuitry.

2. Write 1 to the OSC_32M_CAL_START bit.

3. The ADPD4100/ADPD4101 automatically power up the

high frequency oscillator.

4. The device automatically waits for the high frequency

oscillator to be stable.

5. An internal counter automatically counts the number of

32 MHz high frequency oscillations that occur during

128 cycles of the 1 MHz low frequency oscillator or

4 cycles of the 32 kHz low frequency oscillator, depending

on which low frequency oscillator is enabled based on the

setting of the LFOSC_SEL bit.

6. The OSC_32M_CAL_COUNT bits are updated with the

final count.

7. The 32 MHz oscillator automatically powers down

following calibration unless time slots are active.

8. The device resets the OSC_32M_CAL_START bit

indicating the count has been updated.

The OSC_32M_FREQ_ADJ bits adjust the frequency of the

32 MHz oscillator to the desired frequency. When using an external

low frequency oscillator, the 32 MHz oscillator calibration is per-

formed with respect to the externally provided low frequency

oscillator.

Note that when the calibrations of the low frequency and high

frequency oscillators are complete, set CLK_CAL_ENA = 0 to

disable the clocking of the oscillator calibration circuitry to

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