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ADPD4100 데이터시트(PDF) 74 Page - Analog Devices

부품명 ADPD4100
상세설명  Multimodal Sensor Front End
PDF  101 Pages
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제조업체  AD [Analog Devices]
홈페이지  http://www.analog.com
Logo AD - Analog Devices

ADPD4100 데이터시트(HTML) 74 Page - Analog Devices

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ADPD4100/ADPD4101
Data Sheet
Rev. 0 | Page 74 of 101
Addr
Name
Bits
Bit Name
Description
Reset Access1
0x0002 INT_STATUS_LEV0
[15:12] Reserved
Reserved.
0x0
R
11
INT_LEV0_L
Time Slot L Level 0 interrupt status. This bit is set during a
data register update when the configured criteria is met.
0x0
R/W1C
10
INT_LEV0_K
Time Slot K Level 0 interrupt status. This bit is set during a
data register update when the configured criteria is met.
0x0
R/W1C
9
INT_LEV0_J
Time Slot J Level 0 interrupt status. This bit is set during a
data register update when the configured criteria is met.
0x0
R/W1C
8
INT_LEV0_I
Time Slot I Level 0 interrupt status. This bit is set during a
data register update when the configured criteria is met.
0x0
R/W1C
7
INT_LEV0_H
Time Slot H Level 0 interrupt status. This bit is set during
a data register update when the configured criteria is met.
0x0
R/W1C
6
INT_LEV0_G
Time Slot G Level 0 interrupt status. This bit is set during a
data register update when the configured criteria is met.
0x0
R/W1C
5
INT_LEV0_F
Time Slot F Level 0 interrupt status. This bit is set during a
data register update when the configured criteria is met.
0x0
R/W1C
4
INT_LEV0_E
Time Slot E Level 0 interrupt status. This bit is set during a
data register update when the configured criteria is met.
0x0
R/W1C
3
INT_LEV0_D
Time Slot D Level 0 interrupt status. This bit is set during a
data register update when the configured criteria is met.
0x0
R/W1C
2
INT_LEV0_C
Time Slot C Level 0 interrupt status. This bit is set during a
data register update when the configured criteria is met.
0x0
R/W1C
1
INT_LEV0_B
Time Slot B Level 0 interrupt status. This bit is set during a
data register update when the configured criteria is met.
0x0
R/W1C
0
INT_LEV0_A
Time Slot A Level 0 interrupt status. This bit is set during a
data register update when the configured criteria is met.
0x0
R/W1C
0x0003 INT_STATUS_LEV1
[15:12] Reserved
Reserved.
0x0
R
11
INT_LEV1_L
Time Slot L Level 1 interrupt status. This bit is set during a
data register update when the configured criteria is met.
0x0
R/W1C
10
INT_LEV1_K
Time Slot K Level 1 interrupt status. This bit is set during a
data register update when the configured criteria is met.
0x0
R/W1C
9
INT_LEV1_J
Time Slot J Level 1 interrupt status. This bit is set during a
data register update when the configured criteria is met.
0x0
R/W1C
8
INT_LEV1_I
Time Slot I Level 1 interrupt status. This bit is set during a
data register update when the configured criteria is met.
0x0
R/W1C
7
INT_LEV1_H
Time Slot H Level 1 interrupt status. This bit is set during
a data register update when the configured criteria is met.
0x0
R/W1C
6
INT_LEV1_G
Time Slot G Level 1 interrupt status. This bit is set during a
data register update when the configured criteria is met.
0x0
R/W1C
5
INT_LEV1_F
Time Slot F Level 1 interrupt status. This bit is set during a
data register update when the configured criteria is met.
0x0
R/W1C
4
INT_LEV1_E
Time Slot E Level 1 interrupt status. This bit is set during a
data register update when the configured criteria is met.
0x0
R/W1C
3
INT_LEV1_D
Time Slot D Level 1 interrupt status. This bit is set during a
data register update when the configured criteria is met.
0x0
R/W1C
2
INT_LEV1_C
Time Slot C Level 1 interrupt status. This bit is set during a
data register update when the configured criteria is met.
0x0
R/W1C
1
INT_LEV1_B
Time Slot B Level 1 interrupt status. This bit is set during a
data register update when the configured criteria is met.
0x0
R/W1C
0
INT_LEV1_A
Time Slot A Level 1 interrupt status. This bit is set during a
data register update when the configured criteria is met.
0x0
R/W1C
0x0004 INT_STATUS_TC1
[15:12] Reserved
Reserved.
0x0
R
11
INT_TCLN1_L
Time Slot L Channel 1 ceiling detection interrupt status.
This bit is set during a data register update when
Channel 1 exceeds the threshold level during Time Slot L.
0x0
R/W1C
10
INT_TCLN1_K
Time Slot K Channel 1 ceiling detection interrupt status.
This bit is set during a data register update when
Channel 1 exceeds the threshold level during Time Slot K.
0x0
R/W1C



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