ADPD4100 datasheet(76/101 Pages) AD

76 / 101 page

ADPD4100/ADPD4101

Data Sheet

Rev. 0 | Page 76 of 101

Addr

Name

Bits

Bit Name

Description

Reset Access1

INT_TCLN2_C

Time Slot C Channel 2 ceiling detection interrupt status.

This bit is set during a data register update when

Channel 2 exceeds the threshold level during Time Slot C.

0x0

R/W1C

INT_TCLN2_B

Time Slot B Channel 2 ceiling detection interrupt status.

This bit is set during a data register update when

Channel 2 exceeds the threshold level during Time Slot B.

0x0

R/W1C

INT_TCLN2_A

Time Slot A Channel 2 ceiling detection interrupt status.

This bit is set during a data register update when

Channel 2 exceeds the threshold level during Time Slot A.

0x0

R/W1C

0x0007 INT_ACLEAR

INT_ACLEAR_FIFO

FIFO threshold interrupt autoclear enable. Set this bit to

enable automatic clearing of the FIFO_TH interrupt each

time the FIFO is read.

0x1

R/W

[14:12] Reserved

Reserved.

0x0

INT_ACLEAR_DATA_L

Time Slot L interrupt autoclear enable. Set this bit to

enable automatic clearing of the INT_DATA_L interrupt

each time the Time Slot L data registers are read.

0x1

R/W

INT_ACLEAR_DATA_K

Time Slot K interrupt autoclear enable. Set this bit to

enable automatic clearing of the INT_DATA_K interrupt

each time the Time Slot K data registers are read.

0x1

R/W

INT_ACLEAR_DATA_J

Time Slot J interrupt autoclear enable. Set this bit to

enable automatic clearing of the INT_DATA_J interrupt

each time the Time Slot J data registers are read.

0x1

R/W

INT_ACLEAR_DATA_I

Time Slot I interrupt autoclear enable. Set this bit to

enable automatic clearing of the INT_DATA_I interrupt

each time the Time Slot I data registers are read.

0x1

R/W

INT_ACLEAR_DATA_H

Time Slot H interrupt autoclear enable. Set this bit to

enable automatic clearing of the INT_DATA_H interrupt

each time the Time Slot H data registers are read.

0x1

R/W

INT_ACLEAR_DATA_G

Time Slot G interrupt autoclear enable. Set this bit to

enable automatic clearing of the INT_DATA_G interrupt

each time the Time Slot G data registers are read.

0x1

R/W

INT_ACLEAR_DATA_F

Time Slot F interrupt autoclear enable. Set this bit to

enable automatic clearing of the INT_DATA_F interrupt

each time the Time Slot F data registers are read.

0x1

R/W

INT_ACLEAR_DATA_E

Time Slot E interrupt autoclear enable. Set this bit to

enable automatic clearing of the INT_DATA_E interrupt

each time the Time Slot E data register is read.

0x1

R/W

INT_ACLEAR_DATA_D

Time Slot D interrupt autoclear enable. Set this bit to

enable automatic clearing of the INT_DATA_D interrupt

each time the Time Slot D data registers are read.

0x1

R/W

INT_ACLEAR_DATA_C

Time Slot C interrupt autoclear enable. Set this bit to

enable automatic clearing of the INT_DATA_C interrupt

each time the Time Slot C data registers are read.

0x1

R/W

INT_ACLEAR_DATA_B

Time Slot B interrupt autoclear enable. Set this bit to

enable automatic clearing of the INT_DATA_B interrupt

each time the Time Slot B data registers are read.

0x1

R/W

INT_ACLEAR_DATA_A

Time Slot A interrupt autoclear enable. Set this bit to

enable automatic clearing of the INT_DATA_A interrupt

each time the Time Slot A data registers are read.

0x1

R/W

ADPD4100 데이터시트(PDF) 76 Page - Analog Devices

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