ADPD4100 datasheet(24/101 Pages) AD

24 / 101 page

ADPD4100/ADPD4101

Data Sheet

Rev. 0 | Page 24 of 101

EXECUTION MODES

A state machine in the low frequency oscillator clock domain

controls sleep times, wake-up cycles, and the start of time slot

operations. The low frequency oscillator serves as the time base

for all time slot operations, controls the sample rates, and clocks

the low frequency state machine. This state machine controls all

operations and is controlled by the OP_MODE bit.

Table 15. OP_MODE Bit Setting Descriptions

OP_MODE Setting

Mode

Description

Standby

All operations stopped. Time

slot actions reset. Low power

standby state.

Transitioning to this state from

standby mode starts time slot

operation.

At power-up and following any subsequent reset operations, the

ADPD4100/ADPD4101 are in standby mode. The user can

write 0 to the OP_MODE bit to immediately stop operations

and return to standby mode.

go mode. The user must enter standby mode before changing

the control registers. Standby mode resets the digital portion of

the ADC, all of the pulse generators, and the state machine.

When OP_MODE is set to 1, the device immediately starts the

first wake-up sequence and time slot operations unless using an

external synchronization trigger. If using an external synchroniza-

tion trigger, the device enters the sleep state before the first

wake-up and time slot regions begin.

HOST INTERFACE

The ADPD4100/ADPD4101 provide two methods of communica-

tion with the host, a SPI port and I2C interface. The device also

provides numerous FIFO, data register, error, and threshold

status bits, each of which can be provided by an interrupt function

from a GPIO, read from status registers, or appended as optional

status bytes at the end of a FIFO packet.

Interrupt Status Bits

Data Register Interrupts

The data interrupt status bits, INT_DATA_x for each time slot,

are set every time the data registers for that time slot are

updated. The state of the HOLD_REGS_x bit has no effect on

the interrupt logic.

FIFO Threshold Interrupt

The FIFO threshold interrupt status bit, INT_FIFO_TH, is set

when the number of bytes in the FIFO exceeds the value stored

in the FIFO_TH register. The INT_FIFO_TH bit is cleared

automatically when a FIFO read reduces the number of bytes

below the value in the FIFO_TH register, which allows the user

to set an appropriate data size for their host needs.

Level Interrupts

Two level interrupt status bits, INT_LEV0_x and INT_LEV1_x,

provide an interrupt when the dark data or signal data values

cross above or below a programmed threshold level.

Two comparison circuits are available per time slot. The

INT_LEV0_x or INT_LEV1_x status bits are set when the data

THRESH0_TYPE_x, THRESH0_DIR_x, THRESH0_CHAN_x

settings, or by the associated THRESH1_TYPE_x,

THRESH1_DIR_x, and THRESH1_CHAN_x settings.

The Level 0 interrupt operates as follows. The user sets an 8-bit

threshold value in the THRESH0_VALUE_x bits for the

corresponding time slot. This value is then shifted to the left by

anywhere from 0 bits to 24 bits, specified by the setting of the

THRESH0_SHIFT_x bits. A comparison is then made between

the shifted threshold value and the register chosen by the

THRESH0_TYPE_x bits and the THRESH0_CHAN_x bit. The

INT_LEV0_x status bit is set if the selected data register meets

the criteria set in the THRESH0_DIR_x bits. The Level 1 interrupt

operates in the same fashion.

TIA Ceiling Detection Interrupts

When the TIA ceiling detection is enabled, the TIA ceiling

detection information is latched onto the INT_TCLN1_x bits in

Therefore, the TIA ceiling detection information can be read for

all enabled channels in all enabled time slots separately. The

latched status bits remain set until they are cleared when the

TIA is driven into the region above the threshold, and the

associated status bits turn to 1. Note that these status bits

remain set until they are cleared.

These status bits can be driven to Interrupt X or Interrupt Y by

setting the relevant registers in Table 31, or they can be monitored

by optional status bytes.

Clearing Interrupt Status Bits

All status bits are set regardless of whether the status bit is routed

to one of the interrupt outputs, Interrupt X or Interrupt Y. The

status bits are independent of the interrupt enable bits. The

status bits are always set by the corresponding event. The

interrupt bits stay set until they are either manually or

automatically cleared.

The user can manually clear a given interrupt by writing a 1 to

the matching interrupt status bit. In addition, the data interrupt

status bits can be configured to clear automatically. When the

INT_ACLEAR_DATA_x or INT_ACLEAR_FIFO bit is set, the

appropriate interrupt status bit is automatically cleared when

any matching data register or FIFO register is read. Automatic

clearing of the interrupt status bits removes the need to

manually clear these interrupts.

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