ADPD4100 datasheet(16/101 Pages) AD

16 / 101 page

ADPD4100/ADPD4101

Data Sheet

Rev. 0 | Page 16 of 101

The PAIR12, PAIR34, PAIR56, and PAIR78 bits select whether

the matching input pair is used as two single-ended inputs or as

a differential pair. This selection is valid for all active time slots.

The INP12_x, INP34_x, INP56_x, and INP78_x bits specify

whether the input pair is enabled during the corresponding

time slot and, if enabled, which input is connected to which

AFE channel.

The sleep conditions are used for any inputs that are not enabled.

Sleep conditions are determined by the INP_SLEEP_12,

INP_SLEEP_34, INP_SLEEP_56, and INP_SLEEP_78 bits,

which specify the state for the input pairs during sleep and

when the inputs are not active. Inputs are only considered active

during the precondition and pulse regions for time slots where

they are enabled.

Preconditioning of the sensor connected to the input is provided to

set the operating point at the input just prior to sampling. There

are several different options for preconditioning determined by

the PRECON_x bits. The PRECON_x bits are provided for each

time slot to specify the precondition for enabled inputs or input

pairs during the corresponding time slot. Preconditioning options

include: float the input(s), VC1, VC2, input common-mode

voltage (VICM), TIA_VREF, TIA input, and short the input pair.

The preconditioning time at the start of each time slot is

programmable using the PRE_WIDTH_x bits. The default

preconditioning period is 8 µs.

The block diagram in Figure 17 shows all the bias levels that can

be switched into the input connections during sleep and

preconditioning. These connections are not available during the

sampling phase of a time slot in which the input is selected.

Second AFE Channel

The second AFE channel is disabled by default. When disabled,

the three amplifiers (TIA, BPF, and integrator) are automatically

powered down, and no ADC cycles occur for the second

channel. Digital integration and impulse response mode do not

use the second channel.

The second AFE channel can be enabled with the CH2_EN_x

bits on a per time slot basis. When the second channel is

enabled, ADC conversions and the datapath bits of the second

channel operate. When data is being written to the FIFO, the

Channel 2 data is written after the Channel 1 data.

Channel 2 TIA gain, integrator resistor, and buffer gain (when

in digital integrate or TIA ADC mode) are set separately from

Channel 1.

LED DRIVERS

The ADPD4100/ADPD4101 have four LED drivers, each of

which is brought out to two LED driver outputs providing a

total of eight LED output drivers. The device can drive up to four

LEDs simultaneously, one from each driver pair. The LED output

driver is a current sink. Figure 18 shows an example of a single

LED driver output pair.

LED_CURRENTx_x

LED_DRIVESIDEx_x

LEDxA

LEDxB

VLED1

CVLED

VLED2

CVLED

NOTES

CVLED IS THE BYPASS CAPACITOR.

Figure 18. Block Diagram of LED Driver Output Pair

The LED driver output pins (LED1A, LED1B, LED2A, LED2B,

LED3A, LED3B, LED4A, and LED4B) have a maximum

allowable pin voltage of 3.6 V. Any voltage exposure over this

rating affects the reliability of the device operation and, in

certain circumstances, causes the device to cease proper

operation. The voltage of the LED driver output pins must not

be confused with the supply voltages for the LED themselves.

VLEDx is the voltage applied to the anode of the external LED

whereas the LED output driver pin is connected to the cathode

of the external LED. The compliance voltage is the amount of

headroom voltage at the LED driver pin, measured with respect

to ground, required to maintain the programmed LED current

level and is a function of the current required. Figure 6 shows

the typical compliance voltages required at various LED current

settings for LED driver LED1A, and Figure 19 shows the typical

compliance voltages for all the LED drivers at the maximum LED

current setting. Due to internal layout of the LED driver circuitry,

some drivers output more or less current than others at any

given setting. Typically, the LED1A and LED1B drivers are ~3%

higher than the LED4A and LED4B drivers, respectively, with

the 2× and 3× drivers falling somewhere in between. Also, the

LEDxA drivers are ~3% higher than the LEDxB driver of the

same number.

0.20

0.18

0.16

0.14

0.12

0.10

0.08

0.06

0.04

0.02

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

LED DRIVER VOLTAGE (V)

LED1A

LED1B

LED2A

LED2B

LED3A

LED3B

LED4A

LED4B

Figure 19. LED Driver Current vs. LED Driver Voltage for LED Drivers (LEDxA,

LEDxB) for LED_CURRENTx_x = 0x7F

ADPD4100 데이터시트(PDF) 16 Page - Analog Devices

ADPD4100 데이터시트(HTML) 16 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL