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ADPD4100 데이터시트(PDF) 75 Page - Analog Devices

부품명 ADPD4100
상세설명  Multimodal Sensor Front End
PDF  101 Pages
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제조업체  AD [Analog Devices]
홈페이지  http://www.analog.com
Logo AD - Analog Devices

ADPD4100 데이터시트(HTML) 75 Page - Analog Devices

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Data Sheet
ADPD4100/ADPD4101
Rev. 0 | Page 75 of 101
Addr
Name
Bits
Bit Name
Description
Reset Access1
9
INT_TCLN1_J
Time Slot J Channel 1 ceiling detection interrupt status.
This bit is set during a data register update when
Channel 1 exceeds the threshold level during Time Slot J.
0x0
R/W1C
8
INT_TCLN1_I
Time Slot I Channel 1 ceiling detection interrupt status.
This bit is set during a data register update when
Channel 1 exceeds the threshold level during Time Slot I.
0x0
R/W1C
7
INT_TCLN1_H
Time Slot H Channel 1 ceiling detection interrupt status.
This bit is set during a data register update when
Channel 1 exceeds the threshold level during Time Slot H.
0x0
R/W1C
6
INT_TCLN1_G
Time Slot G Channel 1 ceiling detection interrupt status.
This bit is set during a data register update when
Channel 1 exceeds the threshold level during Time Slot G.
0x0
R/W1C
5
INT_TCLN1_F
Time Slot F Channel 1 ceiling detection interrupt status.
This bit is set during a data register update when
Channel 1 exceeds the threshold level during Time Slot F.
0x0
R/W1C
4
INT_TCLN1_E
Time Slot E Channel 1 ceiling detection interrupt status.
This bit is set during a data register update when
Channel 1 exceeds the threshold level during Time Slot E.
0x0
R/W1C
3
INT_TCLN1_D
Time Slot D Channel 1 ceiling detection interrupt status.
This bit is set during a data register update when
Channel 1 exceeds the threshold level during Time Slot D.
0x0
R/W1C
2
INT_TCLN1_C
Time Slot C Channel 1 ceiling detection interrupt status.
This bit is set during a data register update when
Channel 1 exceeds the threshold level during Time Slot C.
0x0
R/W1C
1
INT_TCLN1_B
Time Slot B Channel 1 ceiling detection interrupt status.
This bit is set during a data register update when
Channel 1 exceeds the threshold level during Time Slot B.
0x0
R/W1C
0
INT_TCLN1_A
Time Slot A Channel 1 ceiling detection interrupt status.
This bit is set during a data register update when
Channel 1 exceeds the threshold level during Time Slot A.
0x0
R/W1C
0x0005 INT_STATUS_TC2
[15:12] Reserved
Reserved.
0x0
R
11
INT_TCLN2_L
Time Slot L Channel 2 ceiling detection interrupt status.
This bit is set during a data register update when
Channel 2 exceeds the threshold level during Time Slot L.
0x0
R/W1C
10
INT_TCLN2_K
Time Slot K Channel 2 ceiling detection interrupt status.
This bit is set during a data register update when
Channel 2 exceeds the threshold level during Time Slot K.
0x0
R/W1C
9
INT_TCLN2_J
Time Slot J Channel 2 ceiling detection interrupt status.
This bit is set during a data register update when
Channel 2 exceeds the threshold level during Time Slot J.
0x0
R/W1C
8
INT_TCLN2_I
Time Slot I Channel 2 ceiling detection interrupt status.
This bit is set during a data register update when
Channel 2 exceeds the threshold level during Time Slot I.
0x0
R/W1C
7
INT_TCLN2_H
Time Slot H Channel 2 ceiling detection interrupt status.
This bit is set during a data register update when
Channel 2 exceeds the threshold level during Time Slot H.
0x0
R/W1C
6
INT_TCLN2_G
Time Slot G Channel 2 ceiling detection interrupt status.
This bit is set during a data register update when
Channel 2 exceeds the threshold level during Time Slot G.
0x0
R/W1C
5
INT_TCLN2_F
Time Slot F Channel 2 ceiling detection interrupt status.
This bit is set during a data register update when
Channel 2 exceeds the threshold level during Time Slot F.
0x0
R/W1C
4
INT_TCLN2_E
Time Slot E Channel 2 ceiling detection interrupt status.
This bit is set during a data register update when
Channel 2 exceeds the threshold level during Time Slot E.
0x0
R/W1C
3
INT_TCLN2_D
Time Slot D Channel 2 ceiling detection interrupt status.
This bit is set during a data register update when
Channel 2 exceeds the threshold level during Time Slot D.
0x0
R/W1C



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