ADPD4100 datasheet(18/101 Pages) AD

18 / 101 page

ADPD4100/ADPD4101

Data Sheet

Rev. 0 | Page 18 of 101

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

100

150

200

250

LED DRIVER CURRENT SETTING (mA)

TWO 528nm LEDs

ONE 850nm LED

Figure 22. Example of the Average LED Forward-Biased Voltage Drop as a

Function of the LED Driver Current Setting

To correctly size the CVLED capacitor, do not deplete it during the

pulse of the LED to the point where the voltage on the capacitor

is less than the forward bias on the LED. Calculate the minimum

value for CVLED as follows:

CVLED = (tLED_PW × ILED_MAX)/(VLED_MIN − (VFB_LED_MAX + VCOMP)) (1)

where:

tLED_PW is the LED pulse width.

ILED_MAX is the maximum forward-biased current on the LED

used in operating the devices.

VLED_MIN is the lowest voltage from the VLEDx supply with no load.

VFB_LED_MAX is the maximum forward-biased voltage required on

the LED to achieve ILED_MAX.

VCOMP is the compliance voltage of the LED driver at the

programmed LED drive level.

The numerator of Equation 1 sets up the total discharge amount

in coulombs from the bypass capacitor to satisfy a single pro-

grammed LED pulse of the maximum current. The denominator

represents the difference between the lowest voltage from the

VLEDx supply and the LED required voltage. The LED required

voltage is the voltage of the anode of the LED such that the compli-

ance of the LED driver and the forward-biased voltage of the

LED operating at the maximum current is satisfied. At a 125 mA

drive current, the compliance voltage of the driver is ~0.4 V. For

a typical ADPD4100/ADPD4101 example, assume that the

lowest value for the VLEDx supply is 4.5 V and that the peak

current is 125 mA for two 528 nm LEDs in parallel. The

minimum value for CVLED is then equal to 1 µF.

CVLED = (3 × 10−6 × 0.125)/(4.5 – (3.5 + 0.4)) = 0.625 nF (2)

As shown in Equation 2, as the minimum supply voltage drops

close to the maximum anode voltage, the demands on CVLED

become more stringent, forcing the capacitor value higher. It is

important to insert the correct values into Equation 2. For

example, using an average value for VLED_MIN instead of the

worst case value for VLED_MIN can cause a serious design

deficiency, resulting in a CVLED value that is too small, causing

insufficient optical power in the application.

Additionally, multiple pulses can cause further droop on the

VLEDx supply if the CVLED capacitor is not fully recharged

between pulses. Therefore, adding a sufficient margin on CVLED

is strongly recommended. Add additional margin to CVLED to

account for multiple pulses and derating of the capacitor value

over voltage, bias, temperature, and other factors over the life of

the component.

DATAPATH, DECIMATION, SUBSAMPLING, AND

FIFO

ADC samples are gathered for each pulse in each time slot and

combine to create a running positive and negative sum for each

time slot. These sums are each kept as a 32-bit unsigned value

sample is added to either the positive or negative sum based on

the SUBTRACT_x bits for the current pulse in standard sampling

mode, or in the lit or dark acquisition regions for digital

integration mode. Figure 23 shows the datapath structure.

ADPD4100 데이터시트(PDF) 18 Page - Analog Devices

ADPD4100 데이터시트(HTML) 18 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL