ADPD4100 datasheet(26/101 Pages) AD

26 / 101 page

ADPD4100/ADPD4101

Data Sheet

Rev. 0 | Page 26 of 101

SPI and I2C Interface

The ADPD4100 contains a SPI port, and the ADPD4101

contains an I2C interface. The SPI and I2C interfaces operate

synchronously with their respective input clocks and require no

internal clocks to operate.

The ADPD4100/ADPD4101 have an internal power-on reset

circuit that sets the device into a known idle state during the

initial power-up. After the power-on reset is released,

approximately 2 μs to 6 μs after the DVDDx supply is active, the

device can be read and written through the SPI or I2C interface.

The registers are accessed using addresses within a 15-bit

address space. Each address references a 15-bit register with one

address reserved for the FIFO read accesses. For both the I2C

and SPI interfaces, reads and writes auto-increment to the next

access sequence. This automatic address increment occurs for

all addresses except the FIFO address, one less than the FIFO

address and the last used address, which is 0x277. Reads from

the FIFO address continue to access the next byte from the FIFO.

SPI Operations

The SPI single register write operation is shown in Figure 26.

The first two bytes contain the 15-bit register address and specifies

that a write is requested. The remaining two bytes are the 16 data

bits to write to the register. The register write occurs only when

all 16 bits are shifted in prior to deassertion of the CS signal.

In addition, multiple registers can be written if additional 16-bit

data is shifted in before deassertion of the CS signal. The

after each 16 bits of data.

The SPI single register read operation is shown in Figure 27.

The first two bytes contain the 15-bit register address and

specifies that a read is requested. Register bits are shifted out

starting with the MSB. In addition, multiple registers can be

read if additional 16-bit data is shifted out prior to deassertion

of the CS signal.

It is recommended that reading from the FIFO is performed

byte wise. There is no requirement to read multiples of 16 bits.

I2C Operations

The ADPD4101 supports fast-mode plus (see the I2C

specification from NXP for more information).

The I2C operations require addressing the device as well as

choosing the register that is being read or written. An I2C

is bidirectional and open drain, where different bit times are

driven in a predetermined way by the master or the slave. The

ADPD4101 acts as a slave on the I2C bus. Start and stop bit

operations are shown as S and P in Figure 28 and Figure 29. The

I2C port supports both 7-bit and 15-bit addresses. If accessing

Address 0x007F or lower, a 7-bit address can be used. If the first

address bit after the slave address acknowledge (ACK) is a 0, a

7-bit address is used, as shown in the short read and write

operations (see Figure 28 to Figure 31). If the first bit after a

slave address acknowledge is 1, a 15-bit address is used as

shown in the long read and write operations (see Figure 32 and

Figure 33).

Figure 28 shows the first half of the short register write operation.

The first byte indicates that the ADPD4101 is being addressed

with a write operation. The ADPD4101 indicates that it has

been addressed by driving an acknowledge. The next byte

operation is a write of the address of the register to be written.

The MSB is the L/S bit (long/short). When this bit is low, a 7-bit

address follows. If the L/S bit is high, a 15-bit address follows.

The ADPD4101 sends an acknowledge following the register

address.

SCLK

MOSI

A14

A13

A12

A11

A10

A9A8A7A6A5A4

D15

D14

D13

D12

D11

D10

D9D8D7D6D5

Figure 26. SPI Write Operation

SCLK

MOSI

MISO

A14

A13

A12

A11

A10

A9A8A7A6A5A4

D14

D15

D13

D12

D11

D10

D5D4D3D2D1D0

Figure 27. SPI Read Operation

MEANS DRIVEN BY ADPD4101

SCL

SDA

GRAY BACKGROUND

SLVA6

SLVA5

SLVA4

SLVA3

SLVA2

SLVA1

SLVA

WRITE

ACK

D15

L/S

Figure 28. I2C Short Write First Half

SCL

D15

D14

D13

D12

D11

D10

ACK

SDA

Figure 29. I2C Short Write Second Half

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