ADPD4100 datasheet(91/101 Pages) AD

91 / 101 page

Data Sheet

ADPD4100/ADPD4101

Rev. 0 | Page 91 of 101

Addr

Name

Bits

Bit Name

Description

Reset Access

[3:0]

INP12_x

IN1 and IN2 input pair enable.

0x0

R/W

0000: input pair disabled. IN1 and IN2 disconnected.

0001: IN1 connected to Channel 1. IN2 disconnected.

0010: IN1 connected to Channel 2. IN2 disconnected.

0011: IN1 disconnected. IN2 connected to Channel 1.

0100: IN1 disconnected. IN2 connected to Channel 2.

0101: IN1 connected to Channel 1. IN2 connected to

Channel 2.

0110: IN1 connected to Channel 2. IN2 connected to

Channel 1.

0111: IN1 and IN2 connected to Channel 1. Single-ended

or differential, based on PAIR12.

1000: IN1 and IN2 connected to Channel 2. Single-ended

or differential, based on PAIR12.

0x0103 CATHODE_A

Reserved

Reserved.

0x0

0x0123 CATHODE_B

[14:12] PRECON_x

Precondition value for enabled inputs during Time Slot x.

0x0

R/W

0x0143 CATHODE_C

000: float input(s).

0x0163 CATHODE_D

001: precondition to VC1.

0x0183 CATHODE_E

010: precondition to VC2.

0x01A3 CATHODE_F

011: precondition to VICM. Used when inputs are

0x01C3 CATHODE_G

configured differentially.

0x01E3 CATHODE_H

100: precondition with TIA input.

0x0203 CATHODE_I

101: precondition with TIA_VREF.

0x0223 CATHODE_J

110: precondition by shorting differential pair.

0x0243 CATHODE_K

[11:10] VC2_PULSE_x

VC2 pulse control for Time Slot x.

0x0

R/W

0x0263 CATHODE_L

00: no pulsing.

01: alternate VC2 on each subsequent Time Slot x.

10: pulse to alternate value specified in VC2_ALT_x using

modulation pulse.

[9:8]

VC2_ALT_x

VC2 alternate pulsed state for Time Slot x.

0x0

R/W

00: VDD.

01: TIA_VREF.

10: TIA_VREF + 215 mV.

11: GND.

[7:6]

VC2_SEL_x

VC2 active state for Time Slot x.

0x0

R/W

00: VDD.

01: TIA_VREF.

10: TIA_VREF + 215 mV.

11: GND.

[5:4]

VC1_PULSE_x

VC1 pulse control for Time Slot x.

0x0

R/W

00: no pulsing.

01: alternate VC1 on each subsequent Time Slot x.

10: pulse to alternate value specified in VC1_ALT_x using

modulation pulse.

[3:2]

VC1_ALT_x

VC1 alternate pulsed state for Time Slot x.

0x0

R/W

00: VDD.

01: TIA_VREF.

10: TIA_VREF + 215 mV.

11: GND.

[1:0]

VC1_SEL_x

VC1 active state for Time Slot x.

0x0

R/W

00: VDD.

01: TIA_VREF.

10: TIA_VREF + 215 mV.

11: GND.

ADPD4100 데이터시트(PDF) 91 Page - Analog Devices

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