ADPD4100 datasheet(46/101 Pages) AD

46 / 101 page

ADPD4100/ADPD4101

Data Sheet

Rev. 0 | Page 46 of 101

Recommended Configurations for ECG Measurement

The following is one of the recommended configurations for

ECG measurement if the dc offset voltage (VDC, see Figure 52) is

negligible or low, less than ±30 mV.

#ADPD4100 ECG Measurement with small DC

offset

0009 0080

# 32MHz oscillator trim

000B 02B2

# 1MHz oscillator trim

000D 0D05

# Sampling rate 300 Hz

000F 0006

# 1MHz low frequency oscillator

0010 0000

# Timeslot A enabled

0020 2220

# Float input 1&2 during sleep

0021 0001

# IN1/IN2 configured as a

differential pair

# Timeslot configuration #

### Timeslot A - Sleep float mode ECG with

multiple charge transfers

0100 0000

# Input resistor 500

Ω

0101 00E6

# skip preconditioning,

bandpass filter bypassed

0102 0007

# IN1&IN2 differential pair to

channel 1

0103 0000

# float during preconditioning

0104 02C1

# TIA gain 100k, Vref = 0.88V

0105 0000

# LEDs off

0106 0000

# LEDs off

0107 0102

# 2 pulses

0108 1000

# float mode, minimum period

010A 0203

# Integrator pulse width,

bandpass filter powered down

010B 01A0

# Integrator pulse timing

offset

010C 0210

# Modulation pulse width and

offset

010D 0000

# Chopping mode disabled

010E 0000

# no ADC offset

010F 0000

# no ADC offset

0110 0003

# Configure number of bytes

written to the registers

If the dc offset voltage is large, use the following recommended

configuration, which can handle up to ±450 mV of dc offset

voltage. There are only three register setting changes, and the

rest is the same as the previous configuration. The input resistor

is changed to 6500 Ω by setting INPUT_R_SELECT_x to 1, TIA

gain is reduced to 25 kΩ by setting TIA_GAIN_CH1_x to 3,

and the number of modulation pulses is increased to 12 by

setting NUM_REPEAT_x to 12.

#ADPD4100 ECG Measurement with high DC

offset

0009 0080

# 32MHz oscillator trim

000B 02B2

# 1MHz oscillator trim

000D 0D05

# Sampling rate 300 Hz

000F 0006

# 1MHz low frequency oscillator

0010 0000

# Timeslot A enabled

0020 2220

# Float inputs 1&2 during sleep

0021 0001

# IN1/IN2 configured as a

differential pair

# Timeslot configuration #

### Timeslot A - Sleep float mode ECG with

multiple charge tran

sfers

0100 0400

# Input resistor 6500

Ω

0101 00E6

# skip preconditioning,

bandpass filter bypassed

0102 0007

# IN1&IN2 differential pair to

channel 1

0103 0000

# float during preconditioning

0104 02C3

# TIA gain 25k, Vref = 0.88V

0105 0000

# LEDs off

0106 0000

# LEDs off

0107 010C

# 12 pulses

0108 1000

# float mode, minimum period

010A 0203

# Integrator pulse width,

bandpass filter powered down

010B 01A0

# Integrator pulse timing

offset

010C 0210

# Modulation pulse width and

offset

010D 0000

# Chopping mode disabled

010E 0000

# no ADC offset

010F 0000

# no ADC offset

0110 0003

# Configure number of bytes

written to the registers

To account for the cases where dc offset voltage is moderate,

different configurations can be utilized. In general, higher dc

offset voltage cases require low TIA gain and 6500 Ω input

resistor selection, whereas lower dc offset voltage cases can use

higher TIA gain and 500 Ω input resistor selection to achieve

the lowest noise performance. In addition, NUM_REPEAT_x

can be increased to allow the full discharge of the sampling

capacitor. Table 28 summarizes the relevant registers for

handling different dc offset voltage levels.

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