ADPD4100 datasheet(44/101 Pages) AD

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ADPD4100/ADPD4101

Data Sheet

Rev. 0 | Page 44 of 101

ECG MEASUREMENT WITH THE

ADPD4100/ADPD4101

The ADPD4100/ADPD4101 can be used for ECG applications

with the simple addition of an external RC network consisting

of two 500 kΩ resistors in series with the inputs and a 470 pF

capacitor across the inputs, as shown in Figure 52. The electrical

equivalent model for an electrode is shown together with the

RC circuit, external to the ADPD4100/ADPD4101.

The 500 kΩ resistors limit the current that can be injected into

or pulled from the body in the case of shorted input pins. The

470 pF capacitor serves as the sensing capacitor for the ECG

signal. The ECG signal is integrated onto the sensing capacitor.

The value of this capacitor is chosen such that an acceptable

SNR is achieved and the time constant of the RC network and

the electrode skin contact allows sufficient charge accumulation

on the sensing capacitor during the sampling period.

The RC network of the 500 kΩ resistors and the 470 pF

capacitor also acts as a low-pass filter, which helps reduce the

high frequency noise due to electrode skin contact.

For multilead ECG measurement, each lead requires a separate

pair of inputs and the RC network of two 500 kΩ resistors and

the 470 pF capacitor, as shown in Figure 52.

TIA

RIN

500kΩ

470pF

ADPD4100/

ADPD4101

INx

VDC

SKIN/ELECTRODE

INTERFACE

NOTES

1. RA is right arm. LA is left arm.

Figure 52. Circuit for Measuring Single-Lead ECG with the

ADPD4100/ADPD4101

Sleep Float Mode

The ADPD4100/ADPD4101 ECG measurement operates in

sleep float mode. Sleep float mode allows a robust ECG

measurement regardless of whether low impedance wet

electrodes or high impedance dry electrodes are used.

In sleep float mode, the sensing capacitor floats all the time

except the charge transfer, accumulating charge from the ECG

signal. The accumulated charge is then transferred into the

ADPD4100/ADPD4101 during a specified time slot for charge

measurement. The device must be configured to float the inputs

for the ECG during the preconditioning period and during

sleep. The inputs are connected to the external capacitor only

during the charge transfer. At all other times, the inputs for the

ECG are floating, resulting in a float time of 1/tP, where tP is the

sampling rate of the ADPD4100/ADPD4101. For example, the

float time in sleep float mode is ~3.3 ms for the sampling rate of

300 Hz.

An advantage of using sleep float in ECG measurements is the

longer charging time for the sensing capacitor. In sleep float

mode, charge accumulation on the sensing capacitor happens

during the sleep and during all other enabled time slots. The

time slot associated with the sleep float mode is only used to

transfer the charge from the sensing capacitor to the ADPD4100/

ADPD4101 amplifier. Sleep float mode also allows the use of

other time slots for different sensor-based applications while

ECG is being measured because the sensing capacitor floats

regardless of the types of applications that the other time slots

enable.

Another advantage of using sleep float mode in ECG measure-

ments is the reduced power consumption and noise. In sleep

float mode, while the sensing capacitor is floating, it is discon-

nected from the amplifier and the amplifier is not powered.

Therefore, sleep float mode reduces the power consumption by

using the passive charging time to transfer the ECG signal from

the body onto the sensing capacitor while the amplifier and all

the later stages are powered down. The passive charging process

of the sampling capacitor associated with sleep float mode also

reduces the noise as the charging process is noise free.

A timing diagram for sleep float mode is shown in Figure 53.

The relevant register settings for sleep float mode are shown in

Table 27.

INTEGRATOR

OUTPUT

INTEGRATOR

SEQUENCE

ADC READ

ACCUMULATED

CHARGE ON CAPACITOR

CONNECT/FLOAT

WAKE

TIME SLOT A (TS A)

SLEEP

TS B

TS X

SEQUENCE TIMING

MOD_WIDTH_x

WAKE

MOD_OFFSET_x

INTEG_OFFSET_x

INTEG_WIDTH_x

START OF TIME SLOT

Figure 53. Sleep Float Mode Timing Diagram

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